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COM20022I 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Product Features
New Features
- - - - - Data Rates up to 10 Mbps Selectable 8/16 Bit Wide Bus With Data Swapper Programmable DMA Channel Programmable Reconfiguration Times 48 Pin TQFP Package
Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory Next ID Readable Internal Clock Scaler and Clock Multiplier for Adjusting Network Speed Operating Temperature Range of -40oC to +85oC Self-Reconfiguration Protocol Supports up to 255 Nodes Supports Various Network Topologies (Star, Tree, Bus...) CMOS, Single +5V Supply Duplicate Node ID Detection Powerful Diagnostics Receive All Packets Mode Flexible Media Interface:
- - Traditional Hybrid Interface For Long Distances up to Four Miles at 2.5Mbps RS485 Differential Driver Interface For Low Cost, Low Power, High Reliability
Ideal for Industrial/Factory/Building Automation and Transportation Applications Deterministic, (ANSI 878.1), Token Passing ARCNET Protocol Minimal Microcontroller and Media Interface Logic Required Flexible Interface For Use With All Microcontrollers or Microprocessors Automatically Detects Type of Microcontroller Interface 2Kx8 On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID
SMSC COM20022I
Page 1
Rev. 08-18-03
DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
ORDERING INFORMATION
Order Number(s): COM20022ITQFP for 48 pin TQFP package
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Rev. 08-18-03
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SMSC COM20022I
DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Revision History
REVISION LEVEL AND DATE 2/25/99 6/8/99 SECTION/FIGURE/ENTRY Section 7.1 - Maximum Guaranteed Ratings*, pg. 57 Figure 9.1 - COM20022I 48 Pin TQFP Package Outline and Table 9.1 COM20022I 48 Pin TQFP Package Parameters, pg. 79 CORRECTION Updated section. Updated figure and table.
SMSC COM20022I
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Rev. 08-18-03
DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Table of Contents
Revision History .......................................................................................................................................... 3
Chapter 1 Chapter 2 Chapter 3 Chapter 4 General Description................................................................................................................ 7 Pin Configuration.................................................................................................................... 8 Description of Pin Functions .................................................................................................. 9 Protocol Description ............................................................................................................. 12
4.1 Network Protocol ........................................................................................................................................12 4.2 Data Rates .................................................................................................................................................12 4.2.1 Selecting Clock Frequencies Above 2.5 Mbps....................................................................................13 4.3 Network Reconfiguration ............................................................................................................................13 4.4 Broadcast Messages..................................................................................................................................14 4.5 Extended Timeout Function .......................................................................................................................14 4.5.1 Response Time ...................................................................................................................................14 4.5.2 Idle Time .............................................................................................................................................14 4.5.3 Reconfiguration Time ..........................................................................................................................14 4.6 Line Protocol ..............................................................................................................................................15 4.6.1 Invitations To Transmit........................................................................................................................15 4.6.2 Free Buffer Enquiries ..........................................................................................................................15 4.6.3 Data Packets.......................................................................................................................................15 4.6.4 Acknowledgements .............................................................................................................................16 4.6.5 Negative Acknowledgements ..............................................................................................................16
Chapter 5
System Description .............................................................................................................. 17
5.1 Microcontroller Interface.............................................................................................................................17 5.1.1 Selection of 8/16-Bit Access ...............................................................................................................20 5.1.2 DMA Transfers To And From Internal RAM ........................................................................................20 5.1.3 DMA Operation ...................................................................................................................................21 5.1.4 DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ........................................................25 5.1.5 DMA Data Transfer Sequence (Memory to I/O: Write A Packet).........................................................25 5.1.6 High Speed CPU Bus Timing Support ................................................................................................25 5.2 Transmission Media Interface ....................................................................................................................26 5.2.1 Traditional Hybrid Interface .................................................................................................................27 5.2.2 Backplane Configuration .....................................................................................................................27 5.2.3 Differential Driver Configuration ..........................................................................................................29 5.2.4 Programmable TXEN Polarity .............................................................................................................29
Chapter 6
Functional Description.......................................................................................................... 31
6.1 Microsequencer..........................................................................................................................................31 6.2 Internal Registers .......................................................................................................................................33 6.2.1 Interrupt Mask Register (IMR) .............................................................................................................33 6.2.2 Data Register ......................................................................................................................................34 6.2.3 Tentative ID Register ..........................................................................................................................34 6.2.4 Node ID Register.................................................................................................................................34 6.2.5 Next ID Register..................................................................................................................................35 6.2.6 Status Register....................................................................................................................................35 6.2.7 Diagnostic Status Register ..................................................................................................................35 6.2.8 Command Register .............................................................................................................................35 6.2.9 Address Pointer Registers ..................................................................................................................35 6.2.10 Configuration Register.....................................................................................................................36 6.2.11 Sub-Address Register .....................................................................................................................36 6.2.12 Setup 1 Register..............................................................................................................................36 6.2.13 Setup 2 Register..............................................................................................................................36 6.3 Bus Control Register ..................................................................................................................................37 6.4 DMA Count Register ..................................................................................................................................37 6.5 Internal RAM ..............................................................................................................................................48 6.5.1 Sequential Access Memory.................................................................................................................48 6.5.2 Access Speed .....................................................................................................................................48 6.6 Software Interface ......................................................................................................................................48 6.6.1 Selecting RAM Page Size ...................................................................................................................49 6.6.2 Transmit Sequence .............................................................................................................................50
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
6.6.3 Receive Sequence ..............................................................................................................................51 6.7 Command Chaining....................................................................................................................................52 6.7.1 Transmit Command Chaining .............................................................................................................52 6.7.2 Receive Command Chaining ..............................................................................................................53 6.8 Reset Details ..............................................................................................................................................54 6.8.1 Internal Reset Logic ............................................................................................................................54 6.9 Initialization Sequence ...............................................................................................................................54 6.9.1 Bus Determination...............................................................................................................................54 6.10 Improved Diagnostics .............................................................................................................................55 6.10.1 Normal Results: ...............................................................................................................................55 6.10.2 Abnormal Results: ...........................................................................................................................56 6.11 Oscillator.................................................................................................................................................56
Chapter 7
7.1 7.2
Operational Description........................................................................................................ 57
Maximum Guaranteed Ratings* .................................................................................................................57 DC Electrical Characteristics......................................................................................................................57
Chapter 8 Chapter 9 Chapter 10
10.1 10.2
Timing Diagrams .................................................................................................................. 60 Package Outline ................................................................................................................... 79 Appendix A ........................................................................................................................... 80
NOSYNC Bit ...........................................................................................................................................80 EF Bit......................................................................................................................................................80
Chapter 11
Appendix B: Example of Interface Circuit Diagram to ISA Bus........................................... 83
List of Figures
Figure 2.1 - COM20022I Pin Configuration ....................................................................................................................8 Figure 3.1 - COM20022I Operation..........................................................................................................................11 Figure 5.1 - Multiplexed, 8051-Like Bus Interface with RS-485 Interface ............................................................18 Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface....................................................19 Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes ...............................................................................22 Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing) ............................................................23 Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................24 Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ................................................................................24 Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode...............................................................................26 Figure 5.8 - COM20022I Network Using RS-485 Differential Transceivers .........................................................28 Figure 5.9 - Dipulse Waveform for Data of 1-1-0 ....................................................................................................28 Figure 5.10 - Internal Block Diagram ........................................................................................................................29 Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing ......................................................................37 Figure 6.2 - Sequential Access Operation ...............................................................................................................47 Figure 6.3 - RAM Buffer Packet Configuration .............................................................................................................50 Figure 6.4 - Command Chaining Status Register Queue .............................................................................................52 Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ..............................................................60 Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ..............................................................61 Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle ...............................................................62 Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ..............................................................63 Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle .....................................................64 Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle .....................................................65 Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle .....................................................66 Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle .....................................................67 Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................68 Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ...............................................................69 Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle....................................................70 Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................71 Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................72 Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................73 Figure 8.15 - TTL Input Timing on XTAL1 Pin........................................................................................................74 Figure 8.16 - Reset and Interrupt Timing ................................................................................................................74
SMSC COM20022I
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DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Figure 8.17 - DMA Timing (Intel Mode 80XX) ........................................................................................................75 Figure 8.18 - DMA Timing (Motorola Mode 68XX) ................................................................................................76 Figure 9.1 - COM20022I 48 Pin TQFP Package Outline..............................................................................................79 Figure 10.1 - Effect of the EF Bit on the TA/RI Bit .................................................................................................82
List of Tables
Table 5.1 - Typical Media .............................................................................................................................................30 Table 6.1 - Read Register Summary............................................................................................................................32 Table 6.2 - Write Register Summary ............................................................................................................................33 Table 6.3 - Status Register ...........................................................................................................................................38 Table 6.4 - Diagnostic Status Register..........................................................................................................................39 Table 6.5 - Command Register.....................................................................................................................................40 Table 6.6 - Address Pointer High Register ....................................................................................................................41 Table 6.7 - Address Pointer Low Register.....................................................................................................................42 Table 6.8 - Sub Address Register .................................................................................................................................42 Table 6.9 - Configuration Register ................................................................................................................................43 Table 6.10 - Setup 1 Register .......................................................................................................................................44 Table 6.11 - Setup 2 Register .......................................................................................................................................45 Table 6.12 - Bus Control Register.................................................................................................................................46 Table 6.13 - DMA Count Register.................................................................................................................................47 Table 8.1 - DMA Timing................................................................................................................................................77 Table 9.1 - COM20022I 48 Pin TQFP Package Parameters........................................................................................79
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer to the ARCNET Local Area Network Standard, or the ARCNET Designer's Handbook, available from Datapoint Corporation.
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SMSC COM20022I
DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 1
General Description
SMSC's COM20022I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments using an ARCNET protocol engine. The small 48 pin package, flexible microcontroller and media interfaces, eight- page message support, and extended temperature range of the COM20022I make it the only true network controller optimized for use in industrial, embedded, and automotive applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it provides a deterministic token-passing protocol, a highly reliable and proven networking scheme, and a data rate of up to 10 Mbps when using the COM20022I. A token-passing protocol provides predictable response times because each network event occurs within a predetermined time interval, based upon the number of nodes on the network. The deterministic nature of ARCNET is essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the 10 Mbps maximum data rate, and the internal diagnostics make the COM20022I the highest performance embedded communications device available. With only one COM20022I and one microcontroller, a complete communications node may be implemented.
SMSC COM20022I
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 2
Pin Configuration
A0/nMUX nRD/nDS nWR/DIR 37 36 35 34 33 32 nCS nDACK nINTR DREQ VDD nRESET VSS nTXEN RXIN N/C BUSTMG nPULSE2 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 nPULSE1 nIOCS16 nREFEX A2/ALE
VDD
VSS
48 AD0 AD1 D10 AD2 D11 VSS D3 VDD D4 D5 VSS D6 1 2 3 4 5 6 7 8 9 10 11 12
47
46
45
44
43
42
41
40
39
38
COM20022I COM20022 48 Pin TQFP 48
VSS
VDD
XTAL1
Ordering Information: COM20022
Ordering Information: COM20022I
PACKAGE TYPE: TQFP PACKAGE TYPE: TQFP TEMP RANGE: (Blank) = Commercial 0C to TEMP RANGE: (Blank) = Commercial: 0C to +70C + 70 I = 1 = Industrial: -40C to +85C Industrial: -40C to +85C
DEVICE TYPE: 20022 = Universal Local Area Network Controller Controller DEVICE TYPE: 20022I = Universal Local Area Network (with 8 RAM) (with 2K x 2K x 8 RAM)
Figure 2.1 - COM20022I Pin Configuration
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XTAL2
VSS
D12
D13
D14
D15
N/C
D7
TC
D9
D8
A1
SMSC COM20022I
DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 3
PIN NO 44,45, 46 NAME
Description of Pin Functions
SYMBOL I/O DESCRIPTION MICROCONTROLLER INTERFACE IN A0/nMUX On a non-multiplexed mode, A0-A2 are address input bits. (A0 is the LSB) On a multiplexed address/data bus, nMUX IN A1 tied Low, A1 is left open, and ALE is tied to the Address Latch Enable signal. A1 is connected to an internal pull-up resistor. IN A2/ALE I/O AD0-AD2, On a non-multiplexed bus, these signals are used as the D3-D7 lower byte data bus lines. On a multiplexed address/data bus, AD0-AD2 act as the address lines (latched by ALE) and as the low data lines. D3-D7 are always used for data only. These signals are connected to internal pull-up resistors. D8-D15 I/O D8-D15 are always used as the higher byte data bus lines only for 16bit internal RAM access. When the 16bit access is disabled, these signals are always Hi-Z. Enabling or disabling the 16bit access is programmable. A data swapper is built in. These signals are connected to internal pull-up resistors. nWR/DIR IN nWR is for 80xx CPU, nWR is Write signal input. Active Low. DIR is for 68xx CPU, DIR is Bus Direction signal input. (Low: Write, High: Read.) nRD/nDS IN nRD is for 80xx CPU, nRD is Read signal input. Active Low. nDS is for 68xx CPU, nDS is Data Strobe signal input. Active Low. nRESET IN Hardware reset signal. Active Low. nINTR OUT Interrupt signal output. Active Low. nCS IN Chip Select input. Active Low. nIOCS16 OUT This signal is an active Low signal which indicates accessing 16bit data only by CPU. This signal becomes active when CPU accesses to data register only if W16 bit is 1. This signal is same as on ISA Bus signal, but it's not OPEN-DRAIN. An external OPEN-DRAIN Buffer is needed when this signal connects to the ISA Bus. BUSTMG IN Read and Write Bus Access Timing mode selecting signal. Status of this signal effects CPU and DMA Timing. L: High speed timing mode (only for non-multiplexed bus) H: Normal timing mode This signal is connected to internal pull-up registers. DREQ OUT DMA Request signal. Active polarity is programmable. Default is active high. nDACK IN DMA Acknowledge signal. Active Low. When BUSTMG is High, this signal is connected to internal pull-up registers TC IN Terminal Count signal. Active polarity is programmable. Default is active high. When BUSTMG is High, this signal is connected to the internal pull-up resistor. nREFEX IN Refresh execution signal. Falling edge detection. This signal is connected to the internal pull-up resistor.
Address 0-2
1,2,4, 7,9, 10,12, 13
Data 0-7
47, 48, 3,5, 14-17
Data 8-15
37
nWrite/ Direction
39
nRead/ nData Strobe nReset In nInterrupt nChip Select nI/O 16 Bit Indicator
31 34 36 42
26
Read/Write Bus Timing Select
33 35 38
DMA Request DMA Ack Terminal Count Refresh Execution
40
SMSC COM20022I
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DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
PIN NO 24
NAME nPulse 1
25
nPulse 2
28 29
Receive In nTransmit Enable
21 22
Crystal Oscillator
8,20, 32,43 6,11, 18,23, 30,41 19,27
Power Supply Ground
SYMBOL I/O DESCRIPTION TRANSMISSION MEDIA INTERFACE nPULSE1 OUT In Normal Mode, these active low signals carry the transmit data information, encoded in pulse format as DIPULSE waveform. In Backplane Mode, the nPULSE1 signal driver is programmable (push/pull or open-drain), while the nPULSE2 I/O nPULSE2 signal provides a clock with frequency of doubled data rate. nPULSE1 is connected to a weak internal pull-up resistor on the open/drain driver in backplane mode. RXIN IN This signal carries the receive data information from the line transceiver. nTXEN OUT Transmission Enable signal. Active polarity is programmable through the nPULSE2 pin. nPULSE2 floating before power-up; nTXEN active low nPULSE2 grounded before power-up; nTXEN active high (this option is only available in Back Plane mode) XTAL1 IN An external crystal should be connected to these pins. Oscillation frequency range is from 10 MHz to 20 MHz. If XTAL2 OUT an external TTL clock is used instead, it must be connected to XTAL1 with a 390ohm pull-up resistor, and XTAL2 should be left floating. VDD PWR +5 Volt power supply pins. VSS PWR Ground pins.
N/C
N/C
Non-connection
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SMSC COM20022I
DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Power On Reconfigure Timer has Timed Out Send Reconfigure Burst
Read Node ID
Write ID to RAM Buffer 1 Set NID=ID
Start Reconfiguration Timer (210 mS)*
Y
Invitation to Transmit to this ID?
N
N
TA?
Y
Y
Free Buffer Enquiry to this ID? N
N Y Y N Write SID to Buffer DID =0? N DID =ID? N Y Write Buffer with Packet Pass the Token Y N N SOH? N
Transmit NAK Transmit ACK N
Y
RI?
RI?
Broadcast? Y Send Packet
Transmit Free Buffer Enquiry N Y ACK? Y N Y
No Activity for 20.5 uS? Y Broadcast Enabled? Y Set NID=ID Start Timer: T=(255-ID) x 36.5 us Activity On Line? N Y
No Activity for 18.7 us? N 1
Y
Was Packet Broadcast? N No Activity for 18.7 us? N N ACK? Y Y
NAK?
Set TA
Set TA
Increment NID Set TMA
Y
No Activity for 18.7 us?
N
CRC OK? Y
N
N
T=0? Y
LENGTH N OK? Y DID =0? N DID =ID? Y SEND ACK N Y Set RI
- ID refers to the identification number of the ID assigned to this node. - NID refers to the next identification number that receives the token after this ID passes it. - SID refers to the source identification. - DID refers to the destination identification. - SOH refers to the start of header character; preceeds all data packets. * Reconfig timer is programmable via setup2 register bits 1, 0. Note - All time values are valid for 10Mbps.
Figure 3.1 - COM20022I Operation
SMSC COM20022I
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DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 4
4.1
Protocol Description
Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM20022I's internal microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the COM20022I's internal RAM buffer, and issuing a command to enable the transmitter. When the COM20022I next receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the transmitter passes the token. Once it has been established that the receiving node can accept the packet and transmission is complete, the receiving node verifies the packet. If the packet is received successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits the COM20022I to generate an interrupt to the processor when selected status bits become true. Figure 2.1 is a flow chart illustrating the internal operation of the COM20022I connected to a 20 MHz crystal oscillator.
4.2
Data Rates
The COM20022I is capable of supporting data rates from 156.25 Kbps to 10 Mbps. The following protocol description assumes a 10 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled or quadrupled by the internal clock multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency. Thus all timeout values are scaled as shown in the following table: Example: IDLE LINE Timeout @ 10 Mbps = 20.5 s. IDLE LINE Timeout for 156.2 Kbps is 20.5 s * 64 = 1.3 ms
INTERNAL CLOCK FREQUENCY 80 MHz 40 MHz 20 MHz
CLOCK PRESCALER Div. by 8 Div. by 8 Div. by 8 Div. by 16 Div. by 32 Div. by 64 Div. by 128
DATA RATE 10 Mbps 5 Mbps 2.5 Mbps 1.25 Mbps 625 Kbps 312.5 Kbps 156.25 Kbps
TIMEOUT SCALING FACTOR (MULTIPLY BY) 1 2 4 8 16 32 64
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SMSC COM20022I
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
4.2.1
Selecting Clock Frequencies Above 2.5 Mbps
To realize a 10 Mbps network, an external 80 MHz clock must be input. However, since 80 MHz is the frequency of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher frequency clocks are generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP[1,0] as shown below. The selected clock is supplied to the ARCNET controller. CKUP1 0 0 1 1 CKUP0 0 1 0 1 CLOCK FREQUENCY (DATA RATE) 20 MHz (Up to 2.5Mbps) Default (Bypass) 40 MHz (Up to 5Mbps) Reserved 80 MHz (Only 10Mbps)
This clock multiplier is powered-down (bypassed) on default. After changing the CKUP1 and CKUP0 bits, the ARCNET core operation is stopped and the internal PLL in the clock generator is awakened and it starts to generate the 40 MHz or 80 MHz. The lock out time of the internal PLL is 8uSec typically. After more than 8 sec (this wait time is defined as 1 msec in this data sheet), it is necessary to write command data '18H' to the command register to re-start the ARCNET core operation. This clock generator is called "clock multiplier". Changing the CKUP1 and CKUP0 bits must be one time or less after releasing a hardware reset. The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.
4.3
Network Reconfiguration
A significant advantage of the COM20022I is its ability to adapt to changes on the network. Whenever a new node is activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new COM20022I is turned on (creating a new active node on the network), or if the COM20022I has not received an INVITATION TO TRANSMIT for 210mS, or if a software reset occurs, the COM20022I causes a NETWORK RECONFIGURATION by sending a RECONFIGURE BURST consisting of eight marks and one space repeated 765 times. The purpose of this burst is to terminate all activity on the network. Since this burst is longer than any other type of transmission, the burst will interfere with the next INVITATION TO TRANSMIT, destroy the token and keep any other node from assuming control of the line. When any COM20022I senses an idle line for greater than 20.5S, which occurs only when the token Is lost, each COM20022I starts an internal timeout equal to 36.5s times the quantity 255 minus its own ID. The COM20022I starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing the destination Node ID. If the timeout expires with no line activity, the COM20022I starts sending INVITATION TO TRANSMIT with the Destination ID (DID) equal to the currently stored NID. Within a given network, only one COM20022I will timeout (the one with the highest ID number). After sending the INVITATION TO TRANSMIT, the COM20022I waits for activity on the line. If there is no activity for 18.7S, the COM20022I increments the NID value and transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If activity appears before the 18.7S timeout expires, the COM20022I releases control of the line. During NETWORK RECONFIGURATION, INVITATIONS TO TRANSMIT are sent to all NIDs (1-255). Each COM20022I on the network will finally have saved a NID value equal to the ID of the COM20022I that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs. When a node is powered off, the previous node attempts to pass the token to it by issuing an INVITATION TO TRANSMIT. Since this node does not respond, the previous node times out and transmits another INVITATION TO TRANSMIT to an incremented ID and eventually a response will be received.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the propagation delay between nodes, and the highest ID number on the network, but is typically within the range of 6 to 15.3 mS.
4.4
Broadcast Messages
Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously. ID zero is reserved for this feature and no node on the network can be assigned ID zero. To broadcast a message, the transmitting node's processor simply loads the RAM buffer with the data packet and sets the DID equal to zero. Figure 5.7 illustrates the position of each byte in the packet with the DID residing at address 0X01 or 1 Hex of the current page selected in the "Enable Transmit from Page fnn" command. Each individual node has the ability to ignore broadcast messages by setting the most significant bit of the "Enable Receive to Page fnn" command (see Table 6.5) to a logic "0".
4.5
Extended Timeout Function
There are three timeouts associated with the COM20022I operation. The values of these timeouts are controlled by bits 3 and 4 of the Configuration Register and bit 5 of the Setup 1 Register.
4.5.1
Response Time
The Response Time determines the maximum propagation delay allowed between any two nodes, and should be chosen to be larger than the round trip propagation delay between the two furthest nodes on the network plus the maximum turn around time (the time it takes a particular COM20022I to start sending a message in response to a received message) which is approximately 3.2 S. The round trip propagation delay is a function of the transmission media and network topology. For a typical system using RG62 coax in a baseband system, a one way cable propagation delay of 7.75 S translates to a distance of about 1 mile. The flow chart in Figure 3.1Figure 2.1 uses a value of 18.7 S (7.75 + 7.75 + 3.2) to determine if any node will respond.
4.5.2
Idle Time
The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 3.1Figure 2.1 illustrates that during a NETWORK RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active node. All other nodes on the network must distinguish between this operation and an entirely idle line. During NETWORK RECONFIGURATION, activity will appear on the line every 20.5 S. This 20.5 S is equal to the Response Time of 18.7 S plus the time it takes the COM20022I to start retransmitting another message (usually another INVITATION TO TRANSMIT).
4.5.3
Reconfiguration Time
If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate over longer distances than the 1 mile stated earlier. The logic levels on these bits control the maximum distances over which the COM20022I can operate by controlling the three timeout values described above. For proper network operation, all COM20022I's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration Time.
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4.6
Line Protocol
The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval and ended with a stop interval. Unlike asynchronous protocols, there is a constant amount of time separating each data byte. On a 10 Mbps network, each byte takes exactly 11 clock intervals of 100ns each. As a result, one byte is transmitted every 1.1 S and the time to transmit a message can be precisely determined. The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 50nS duration. A transmission starts with an ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent, with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of transmission can be performed as described below:
4.6.1
Invitations To Transmit
An Invitation To Transmit is used to pass the token from one node to another and is sent by the following sequence: An ALERT BURST An EOT (End Of Transmission: ASCII code 04H) Two (repeated) DID (Destination ID) characters ALERT BURST EOT DID DID
4.6.2
Free Buffer Enquiries
A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the following sequence: An ALERT BURST An ENQ (ENQuiry: ASCII code 85H) Two (repeated) DID (Destination ID) characters ALERT BURST ENQ DID DID
4.6.3
Data Packets
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence: An ALERT BURST An SOH (Start Of Header--ASCII code 01H) An SID (Source ID) character Two (repeated) DID (Destination ID) characters A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is sent, or 00H followed by a COUNT character if a long packet is sent. N data bytes where COUNT = 256-N (or 512-N for a long packet) 16 15 2 Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X + X + X + 1.
ALERT BURST
SOH
SID
DID
DID
COUNT
data
data
CRC
CRC
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4.6.4
Acknowledgements
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST An ACK (ACKnowledgement--ASCII code 86H) character ALERT BURST ACK
4.6.5
Negative Acknowledgements
A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character ALERT BURST NAK
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Chapter 5
5.1
System Description
Microcontroller Interface
The top halves of Figure 5.1 and Figure 5.2 illustrate typical COM20022I interfaces to the microcontrollers. The interfaces consist of a 8-bit data bus, an address bus and a control bus. In order to support a wide range of microcontrollers without requiring glue logic and without increasing the number of pins, the COM20022I automatically detects and adapts to the type of microcontroller being used. Upon hardware reset, the COM20022I first determines whether the read and write control signals are separate READ and WRITE signals (like the 80XX) or DIRECTION and DATA STROBE (like the 68XX). To determine the type of control signals, the device requires the software to execute at least one write access to external memory before attempting to access the COM20022I. The device defaults to 80XX-like signals. Once the type of control signals are determined, the COM20022I remains in this interface mode until the next hardware reset occurs. The second determination the COM20022I makes is whether the bus is multiplexed or nonmultiplexed. To determine the type of bus, the device requires the software to write to an odd memory location followed by a read from an odd location before attempting to access the COM20022I. The signal on the A0 pin during the odd location access tells the COM20022I the type of bus. Since multiplexed operation requires A0 to be active low, activity on the A0 line tells the COM20022I that the bus is nonmultiplexed. The device defaults to multiplexed operation. Both determinations may be made simultaneously by performing a WRITE followed by a READ operation to an odd location within the COM20022I Address space 20022 registers. Once the type of bus is determined, the COM20022I remains in this interface mode until hardware reset occurs. Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be changed until hardware reset. Refer to Description of Pin Functions section for details on the related signals. All accesses to the internal RAM and the internal registers are controlled by the COM20022I. The internal RAM is accessed via a pointer-based scheme (refer to the Sequential Access Memory section), and the internal registers are accessed via direct addressing. Many peripherals are not fast enough to take advantage of high-speed microcontrollers. Since microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access time. The access time of the COM20022I, on the other hand, is so fast that it does not need to limit the speed of the microcontroller. The COM20022I is designed to be flexible so that it is independent of the microcontroller speed. The COM20022I provides for no wait state arbitration via direct addressing to its internal registers and a pointer based addressing scheme to access its internal RAM. The pointer may be used in auto-increment mode for typical sequential buffer emptying or loading, or it can be taken out of auto-increment mode to perform random accesses to the RAM. The data within the RAM is accessed through the data register. Data being read is prefetched from memory and placed into the data register for the microcontroller to read. It is important to notice that only by writing a new address pointer (writing to an address pointer low), one obtains the contents of COM20022I internal RAM. Performing only read from the Data Register does not load new data from the internal RAM. During a write operation, the data is stored in the data register and then written into memory. Whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepare for the first read operation.
SMSC COM20022I
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DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
XTAL1 XTAL2 AD0-AD7 ALE A15 RESET nRD nWR nINT1
COM2002I
AD0-AD2, D3-D7 A2/BALE nCS nRESET nRD/nDS nWR/DIR nINTR nTXEN nPULSE1 nPULSE2 GND Differential Driver Configuration 75176B or Equiv. RXIN
8051
A0/nMUX XTAL1 XTAL2
* Media Interface may be replaced with Figure A, B or C. 27 pF
27 pF
20 MHz XTAL
+5V RXIN +5V RXIN
2 6 7 Receiver HFD3212-002
100 Ohm TXEN nPULSE1 nPULSE2 GND nPULSE1 +5V
2 6 7 Transmitter 3 HFE4211-014
2 Fiber Interface (ST Connectors) BACKPLANE CONFIGURATION NOTE: COM20022I must be in backplane
FIGURE A
FIGURE B
Figure 5.1 - Multiplexed, 8051-Like Bus Interface with RS-485 Interface
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
XTAL1 XTAL2 D0-D7 A0 A1 A2 A7 nRES nIOS R/nW nIRQ1 D0-D7 A0/nMUX A1 A2/BALE nCS nRESET nRD/nDS
COM20022I
RXIN 75176B or Equiv.
TXEN nPULSE1 nPULSE2 GND
nWR/nDIR nINTR
Differential Driver Configuration * Media Interface may be replaced with Figure A, B or C.
6801
XTAL1 XTAL2 27 pF
27 pF
20MHz XTAL
+5V HYC9068 or HYC9088 RXIN RXIN 6 10 uF + 0.47 uF
12 nTXEN nPULSE1 nPULSE2 GND N/C nPULSE1 nPULSE2 17, 19, 4, 13, 14 3 0.47 uF -5V Traditional Hybrid Configuration *Valid for 2.5 Mbps only. 11 5.6K 1/2W 5.6K 1/2W 0.01 uF 1KV
+ 10 uF
FIGURE C
Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
5.1.1
Selection of 8/16-Bit Access
The interface to the internal RAM is software selectable as either 8 or 16-bit. This feature is new to the COM20022I. The D15-D8 pins are the upper-byte data bus pins. The nIOCS16 pin is the 16-bit I/O access enable output pin. This pin is active low for a 16-bit RAM access by the CPU (not a DMA access). The 16-bit access mode is enabled and disabled through the W16 bit located in the Bus Control Register at bit 7. The SWAP bit is used to swap the upper and lower data bytes in 16-bit mode, as shown in the table below. The SWAP bit is located at bit 0 of Address Low Pointer. This location is same as the A0 bit; when 16 bit access is enabled (W16 =1), the A0 bit becomes the SWAP bit.
DETECTED HOST I/F MODE Intel 80xx Mode (RD,WR Mode) Motorola 68xx Mode (DIR, DS Mode) Note:
SWAP BIT (NOTE) 0 1 0 1
D15-D8 PINS Odd Even Even Odd
D7-D0 PINS Even Odd Odd Even
The SWAP bit is undefined after a hardware reset As shown on the table above, even address data is to/from D7-D0 pins and odd address data is to/from D15-D8 pins when detected host interface mode is Intel 80xx mode and the SWAP bit is not set. The odd address data is to/from the D7-D0 pins and the even address data is to/from D15-D8 pins when detected host interface mode is Motorola 68xx mode and the SWAP bit is not set. When disabling 16-bit access, the D15-D8 pins are always Hi-Z. The D15-D8 pins are Hi-Z when enabling 16-bit access except for internal RAM access. W16 bit and SWAP bit influence both the CPU cycle and DMA cycle.
5.1.2
DMA Transfers To And From Internal RAM
The COM20022I supports DMA transfers to and from the internal RAM. This feature is new to the COM20022I. The software selectable 8/16 bit interface to the RAM pertains to DMA transfers. When the W16 bit=0, the microcontroller interface and DMA transfers are both 8-bit data transfers to/from internal RAM. When W16=1 they are both 16-bit data transfers. An 8-bit microcontroller interface and 16-bit DMA data transfer cannot be selected; they must be the same width data transfers to/from internal RAM. The data swapping operation on 16-bit data transfers also pertains to both. The DMA interface consists of several added pins. The DREQ pin is the DMA Request output pin. The active polarity of this pin is programmable; the default is active-high. The nDACK pin is the active-low DMA acknowledge input pin. The TC pin is the external terminal count input pin. This pin determines when the nDACK pin is active. It's active polarity is programmable; the default is active-high. The nREFEX pin is the active-low refresh execution pulse input pin. The DMA interface is controlled by the following bits. The DMAEND bit selects whether or not to mask the interrupt upon finishing the DMA. This bit is located at bit 4 of the Mask register. The DMAEN bit is used to disable/enable the assertion of the DMA Request (DREQ pin) after writing the Address Pointer Low register. This bit is located in the Address Pointer High register, bit 3. The following bits are located in the Bus Control Register: DRPOL, TCPOL and DMAMD[1,0]. The DRQPOL bit sets the active polarity of the DREQ pin; the TCPOL bit sets the active polarity of the TC pin; the DMAMD[1,0] bits select the data transfer mode of the DMA. The ITCEN/RTRG bit has one of two functions, depending on the DMA transfer mode selected. ITCEN is the Internal Terminal Counter Enable. It is used to select whether the DMA is terminated by external TC
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only or by either internal or external TC. ITCEN is for Non-Burst or Burst mode. RTRG selects the retrigger mode as either external or internal. It is for the two Programmable-Burst modes. The TC8/RSYN/GTTM bit has one of three functions, depending on the DMA transfer mode selected. TC8 is bit 8 of the Terminal Count. It is the MSB of the 9 bit Terminal Count setting register (the other 8 bits are in the DMA Count register). TC8 is for Non-Burst or Burst mode. RSYN is the Refresh Synchronous bit. This bit is used to select whether the DMA is started immediately or after Refresh execution. GTTM is the Gate Time bit. This bit selects whether the Gate Time is 350nS (min) or 750nS (min). RSYN and GTTM are for the two Programmable-Burst modes. RSYN is for External Re-Trigger mode; GTTM is for internal Re-Trigger mode. Located in the DMA Count Register, the TC7-TC0 /TIM7-TIM0 /CYC7-CYC0 bits have one of three functions depending on the DMA transfer mode. TC7-TC0 are for non-burst or burst mode. These are the lower 8 bits of the Terminal Count setting register (the MSB is in the Bus Control Register). The TIM7TIM0 bits are for setting the time of the continuous DMA transfer in Programmable-Burst by Timer mode. The CYC7-CYC0 bits are for setting the time of the continuous DMA transfer in Programmable-Burst by Cycle mode.
5.1.3
DMA Operation
The DMA interface operates in one of four transfer modes: Non-Burst, Burst, Programmable-Burst (by timer) and Programmable-Burst (by cycle counter). The data transfer mode of the DMA is selected through the DMAMD[1,0] bits in the Bus Control register, bits [3,2]. These modes are described below. Non-Burst mode is a Single Transfer mode wherein, the DREQ pin is asserted after writing the Address Pointer Low Register when DMAEN=1. Actually, DREQ pin is asserted 4TARB time after writing the Address Pointer Low Register when DMAEN = 1 (refer to Figure 5.3). This mode operates as follows: 1. 2. 3. 4. The nDACK pin is asserted by the DMA Controller detecting the DREQ pin asserted. The DREQ pin is deasserted by the COM20022I detecting the nDACK pin asserted. The nDACK pin is deasserted by the DMA Controller detecting the DREQ pin deasserted after executing the present read or write cycle. The DREQ pin is asserted by the COM20022I detecting the DACK pin deasserted.
Repeat above 4 steps until the TC pin goes active. This mode is called "Cycle steal mode". Burst mode is a Demand Transfer mode. In this mode, the DREQ pin is asserted after writing the Address Pointer Low Register when DMAEN=1. Actually, DREQ pin is asserted 4TARB time after writing the Address Pointer Low Register when DMAEN = 1 (refer to Figure 5.3). The DACK pin is asserted by the DMA Controller detecting the DREQ pin asserted. The DREQ pin stays asserted until the TC pin goes High. Programmable-Burst mode is a Demand Transfer mode with temporary DREQ deassertion for a Refresh cycle. The DREQ pin is asserted after writing the Address Pointer Low Register when DMAEN=1 (refer to Figure 5.3). The DACK pin is asserted by the DMA Controller detecting the DREQ pin asserted. If the continuous DMA operation time is longer than the set Refresh period, then DREQ is deasserted. The DREQ is held deasserted after negating nDACK for the Gate time. After the Gate time, the DREQ pin is asserted again. The DREQ pin stays asserted until the TC pin goes High. In Programmable-Burst mode, the gating can be by timer or by cycle counter.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
DREQ nWR
DMAEN bit minimum 4TARB
Writing Address Pointer Low
TARB is the ARBITRATION Clock Period. It depends on the TOPR and SLOW-ARB bit. TOPR is the period of operation clock frequency (output of the clock multiplier). It depends on the CKUP1 and CKUP0 bits. TARB = TOPR @ SLOW-ARB = 0 TARB = 2 TOPR @ SLOW-ARB = 1
Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes
As an example of gating by cycle, in an ISA bus system, the Refresh period is 15S. Continuous transfer by DMA must be less than 15S to prevent blocking by the Refresh cycle. A DMA cycle of consecutive DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5S. The Refresh execution time is 500nS. This computes to 15S - 2.5S - 500nS = 12S or 12 cycles. Therefore the DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the ProgrammableBurst mode DMA transfer.
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DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Gate Time DREQ (Active-High) nDACK (Active-Low) Transfer term (Counting Read/Write pulse or counting internal timer) Restart Transfer
Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing)
The timing of the Non-Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet. The basic sequence of operation is as follows: nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=1). DREQ becomes inactive after nDACK and read/write signal become active. DREQ becomes active after nDACK or read/write signal becomes inactive. DREQ becomes inactive after TC and the read/write signal assert (when nDACK=0). In this case, DREQ doesn't become active again after nDACK becomes inactive. nDACK becomes inactive after DREQ=0 and the present cycle finishes.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration purposes. Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing
DREQ
nDACK
Read/Write Signal
TC
The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet. The basic sequence of operation is as follows: nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN= "1"). DREQ becomes inactive after TC asserts (when nDACK= "0"). In this case, DREQ doesn't become active again after nDACK becomes inactive. nDACK becomes inactive after DREQ= 0 and the present cycle finishes. The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration purposes.
DREQ nDACK
Read/Write Signal
TC
Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing
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The following sequences show the data transfer for a DMA read and a DMA write. The transfer of data between system memory and internal RAM functions as a memory to I/O DMA transfer. Since it is treated as an I/O device, the COM20022I has to create the RAM address. Therefore the COM20022I's address pointers must be programmed before starting the DMA transfers.
5.1.4
DMA Data Transfer Sequence (I/O to Memory: Read A Packet)
step1: Set DMA-controller (ex. 8237) step2: Set DRQPOL, TCPOL, DMAMD1 and DMAMD0 bits >>Finished DMA SETUP >>A packet received step3: Set address, byte count and etc. of DMA controller step4: Set pointer High and Low (RDDATA=1,AUTOINC=1, DMAEN=0) step5: Read SID, DID, CP in the received packet step6: Set DMAEN=1 (RDDATA=1, AUTOINC=1) step7: DMAEND=1 in Mask REG. step8: Set pointer = CP >>DREQ is asserted by step8 >>Interrupt occurs upon finishing DMA
5.1.5
DMA Data Transfer Sequence (Memory to I/O: Write A Packet)
step1: Set DMA-controller (ex. 8237) step2: Set DRQPOL, TCPOL, DMAMD1 and DMAMD0 bits >>Finished DMA SETUP step3: Set address, byte count and etc. of DMA controller step4: Set pointer High and Low (RDDATA=0,AUTOINC=1, DMAEN = 0) step5: Write SID,DID,CP in the sending packet step6: Set DMAEN=1 (RDDATA=0, AUTOINC=1) step7: DMAEND=1 in Mask REG. step8: Set pointer = CP >>DREQ is asserted by step8 >>Interrupt occurs upon finishing DMA transfer step9: Write Enable Transmit command to command register
5.1.6
High Speed CPU Bus Timing Support
High speed CPU bus support was added to the COM20022I. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these timings. For example, a RISC type single chip microcontroller (like the HITACHI SH-1 series) changes I/O address at the same time as the read signal. Therefore, several external logic ICs would be required to connect to this microcontroller. In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal DIAG register read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read (nRD) signals. The decoder will generate a noise spike at the above tight timing. The DIAG register is cleared by the spike signal without reading itself. This is unexpected operation. Reading the internal RAM and Next Id Register have the same mechanism as reading the DIAG register. Therefore, the address decode and host interface mode blocks were modified to fit the above CPU interface to support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address (A2-A0) and Chip Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal delayed nRD signal. The internal real read signal is the more delayed nRD signal. But the rising edge of nRD doesn't delay. By this modification, the internal real address and Chip Select are stable while the internal real read signal is active. Refer to Figure 5.7 on the following page.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
A2-A0, nCS
VALID
nRD
Delayed nRD (nRD1)
Sampled A2-A0, nCS More delayed nRD (nRD2)
VALID
Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled. Also, the nRD signal is not delayed, because the above sampling and delaying paths decrease the data access time of the read cycle. The above sampling and delaying signals are supplied to the Read Pulse Generation logic which generates the clearing pulse for the Diagnostic register and generates the starting pulse of the RAM Arbitration. Typical delay time between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is around 10nS. Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some wait cycles to extend the width without any impact on performance. The BUSTMG pin is used to support this function. It is used to Enable/Disable the High Speed CPU Read and Write function. It is defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled if the RBUSTMG bit is 0. If BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled (see definition of RBUSTMG bit below). The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as: RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled. In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply. BUSTMG PIN 0 1 1 RBUSTMG BIT X 0 1 BUS TIMING MODE High Speed CPU Read and Write Normal Speed CPU Read and Write High Speed CPU Read and Normal Speed CPU Write
5.2
Transmission Media Interface
The bottom halves of Figure 5.1 and Figure 5.2 illustrate the COM20022I interface to the transmission media used to connect the node to the network. Table 5.1 lists different types of cable which are suitable for ARCNET applications. The user may interface to the cable of choice in one of three ways:
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
5.2.1
Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid Interface is recommended if the node is to be placed in a network with other Hybrid-Interfaced nodes. The Traditional Hybrid Interface is for use with nodes operating at 2.5 Mbps only. The transformer coupling of the Hybrid offers isolation for the safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20022I. The COM20022I transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2. Lack of pulses indicates a logic "0". The nPULSE1 and nPULSE2 signals are sent to the Hybrid, which creates a 200nS dipulse signal on the media. A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse appearing on the media is coupled through the RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the COM20022I. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN pulses occur at multiples of 400nS. The COM20022I can tolerate distortion of plus or minus 100nS and still correctly capture and convert the RXIN pulses to NRZ format. Figure 5.4 illustrates the events which occur in transmission or reception of data consisting of 1, 1, 0.
5.2.2
Backplane Configuration
The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications like backplanes and instrumentation. This mode is advantageous because it saves components, cost, and power. Since the Backplane Configuration encodes data differently than the traditional Hybrid Configuration, nodes utilizing the Backplane Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. The Backplane Configuration does not isolate the node from the media nor protects it from Common Mode noise, but Common Mode Noise is less of a problem in short distances. The COM20022I supplies a programmable output driver for Backplane Mode operation. A push/pull or open drain driver can be selected by programming the P1MODE bit of the Setup 1 Register (see register descriptions for details). The COM20022I defaults to an open drain output. The Backplane Configuration provides for direct connection between the COM20022I and the media. Only one pull-up resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each individual node). The nPULSE1 signal, in this mode, is an open drain or push/pull driver and is used to directly drive the media. It issues a 200nS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20022I does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of the resistor required on the media for open drain mode.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
RT
+VCC +VCC RBIAS +VCC RBIAS RBIAS
RT
75176B or Equiv. COM20022I COM20022I
COM20022I
Figure 5.8 - COM20022I Network Using RS-485 Differential Transceivers
20MHZ CLOCK (FOR REF. ONLY) nPULSE1
100ns 100ns
1
1
0
nPULSE2
200ns
DIPULSE
400ns
RXIN
Figure 5.9 - Dipulse Waveform for Data of 1-1-0
In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor. The RXIN signal is directly connected to the cable via an internal Schmitt trigger. A negative pulse on this input indicates a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane applications, RXIN is connected to nPULSE1 to make the serial backplane data line. A ground line (from the coax or twisted pair) should run in parallel with the signal. For applications requiring different treatment of the receive signal (like filtering or squelching), nPULSE1 and RXIN remain as independent pins. External differential drivers/receivers for increased range and common mode noise rejection, for example, would require the signals to be independent of one another. When the device is in Backplane Mode, the clock provided by the nPULSE2 signal may be used for encoding the data into a different encoding scheme or other synchronous operations needed on the serial data stream.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
5.2.3
Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled configuration recommended for applications like car-area networks or other cost-sensitive applications which do not require direct compatibility with existing ARCNET nodes and do not require isolation. The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the node from the media. The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable and the COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20022I is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive.
5.2.4
Programmable TXEN Polarity
To accommodate transceivers with active high ENABLE pins, the COM20022I contains a programmable TXEN output. To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected to ground. To retain the normal active low polarity, nPULSE2 should be left open. The polarity determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is desired.
A0/nMUX A1 A2/BALE
ADDRESS DECODING CIRCUITRY
2K x 8 RAM ADDITIONAL REGISTERS
nIOCS16 AD0-AD2, D3-D15 STATUS/ COMMAND REGISTER
nINTR
nRESET
RESET LOGIC
MICROSEQUENCER AND WORKING REGISTERS
TX/RX LOGIC
nPULSE1 nPULSE2 nTXEN RXIN
OSCILLATOR nRD/nDS nWR/DIR nCS BUS ARBITRATION CIRCUITRY
XTAL1 XTAL2
RECONFIGURATION TIMER
NODE ID LOGIC
DMA
DREQ nDACK TC nREFEX
Figure 5.10 - Internal Block Diagram
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Table 5.1 - Typical Media CABLE TYPE NOMINAL IMPEDANCE ATTENUATION PER 1000 FT. AT 5 MHZ 5.5dB
RG-62 Belden #86262 RG-59/U Belden #89108 RG-11/U Belden #89108 IBM Type 1* Belden #89688 IBM Type 3* Telephone Twisted Pair Belden #1155A COMCODE 26 AWG Twisted Pair Part #105-064-703
Note*:
93 75 75 150 100 105
7.0dB 5.5dB 7.0dB 17.9dB 16.0dB
Non-plenum-rated cables of this type are also available.
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Chapter 6
6.1
Functional Description
Microsequencer
The COM20022I contains an internal microsequencer which performs all of the control operations necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic. The COM20022I derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier. These clocks provide the rate at which the instructions are executed within the COM20022I. The 20 MHz clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which the instructions are executed. The microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers. One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is decoded by the internal instruction decoder, at which point the COM20022I proceeds to execute the instruction. When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is loaded with the jump address from the ROM. The COM20022I contains an internal reconfiguration timer which interrupts the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of the Diagnostic Status Register is set.
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Table 6.1 - Read Register Summary READ REGISTER STATUS DIAG. STATUS ADDRESS PTR HIGH ADDRESS PTR LOW DATA* SUB ADR CONFIGURATION TENTID NODE ID SETUP1 NEXT ID SETUP2 BUS CONTROL MSB RI/TRI LSB TA/ TTA X ADDR 00 01 02 03 04 05 06 07-0 07-1 07-2 07-3 07-4 07-5
X/RI DUPID AUTOINC A6 D6 0 CCHEN TID6 NID6 FOUR NAKS NXT ID6 X X
X/TA RCVACT X A5 D5 0 TXEN TID5 NID5 X NXT ID5 CKUP1 ITCEN/ RTRG TC5/ TIM5/ CYC5
POR TOKEN X A4 D4 0 ET1 TID4 NID4 RCVALL NXT ID4 CKUP0 TC8/ RSYN/ GTTM TC4/ TIM4/ CYC4
TEST EXCNAK DMAEN A3 D3 (R/W)* ET2 TID3 NID3 CKP3 NXT ID3 EF DMAMD1 TC3/ TIM3/ CYC3
RECON TENTID A10 A2 D2 SUBAD2 BACKPLANE TID2 NID2 CKP2 NXT ID2 NOSYNC DMAMD0 TC2/ TIM2/ CYC2
TMA
NEW NEXTID
MYRECON RDDATA A7 D7 (R/W)* RESET TID7 NID7 P1 MODE NXT ID7 RBUSTMG W16
A9 A1 D1 SUBAD1 SUBAD1 TID1 NID1 CKP1 NXT ID1 RCNTM1 TCPOL
A8 A0/ SWAP D0 SUBAD0 SUBAD0 TID0 NID0 SLOWARB NXT ID0 RCMTM2 DRQPOL TC0/ TIM0/ CYC0
DMA COUNT
Note*:
TC7/ TIM7/ CYC7
TC6/ TIM6/ CYC6
TC1/ TIM1/ CYC1
07-6
This bit can be written and read.
*DATA REGISTER AT 16 BIT ACCESS BIT BIT BIT BIT BIT REGISTER
15 14 13 12 11
BIT 10 D 10
BIT 9 D9
BIT 8 D8
BIT 7 D7
BIT 6 D6
BIT 5 D5
BIT 4 D4
BIT 3 D3
BIT 2 D2
BIT 1 D1
BIT 0 D0
ADDR 04
DATA
D 15
D 14
D 13
D 12
D 11
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Table 6.2 - Write Register Summary WRITE ADDR 00 01 02 03 04 05 06 07-0 07-1 07-2 07-3 07-4 07-5 MSB RI/TR1 LSB TA/ TTA C0 A8 REGISTER
INTERRUPT MASK
0 C6 AUTOINC A6 D6 0 CCHEN TID6 NID6 FOUR NAKS 0 0 0
0 C5 0 A5 D5 0 TXEN TID5 NID5 0 0 CKUP1 ITCEN/ RTRG TC5/ TIM5/ CYC5
C7 RDDATA A7 D7 (R/W)* RESET TID7 NID7 P1MODE 0 RBUSTMG W16
DMA END C4 0 A4 D4 0 ET1 TID4 NID4 RCVALL 0 CKUP0 TC8/ RSYN/ GTTM TC4/ TIM4/ CYC4
EXCNAK C3 DMAEN A3 D3 (R/W)* ET2 TID3 NID3 CKP3 0 EF DMAMD1 TC3/ TIM3/ CYC3
RECON
NEW NEXTID
C2 A10 A2 D2 SUBAD2 BACKPLANE TID2 NID2 CKP2 0 NOSYNC DMAMD0 TC2/ TIM2/ CYC2
C1 A9 A1 D1 SUBAD1 SUBAD1 TID1 NID1 CKP1 0 RCNTM1 TCPOL TC1/ TIM1/ CYC1
COMMAND
A0/ SWAP D0 SUBAD0 SUBAD0 TID0 NID0
SLOWARB
ADDRESS PTR HIGH ADDRESS PTR LOW DATA* SUBADR CONFIGURATION TENTID NODEID SETUP1 TEST SETUP2 BUS CONTROL DMA COUNT
0 RCNTM0 DRQPOL TC0/ TIM0/ CYC0
07-6
TC7/ TIM7/ CYC7
TC6/ TIM6/ CYC6
Note*:
This bit can be written and read.
*DATA REGISTER AT 16 BIT ACCESS BIT BIT BIT BIT BIT REGISTER
15 14 13 12 11
BIT 10 D 10
BIT 9 D9
BIT 8 D8
BIT 7 D7
BIT 6 D6
BIT 5 D5
BIT 4 D4
BIT 3 D3
BIT 2 D2
BIT 1 D1
BIT 0 D0
ADDR 04
DATA
D 15
D 14
D 13
D 12
D 11
6.2
Internal Registers
The COM20022I contains 16 internal registers. Table 6.1 and Table 6.2 illustrate the COM20022I register map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1
Interrupt Mask Register (IMR)
The COM20022I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I), New Next
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ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. DMAEND bit is inverted DMAEN bit on ADDRESS PTR High register. No other Status or Diagnostic Status bits can generate an interrupt. The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. If the DMAEND bit is not masked, the interrupt occurs by finishing the DMA operation. The Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset.
6.2.2
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the Data Register is loaded with the contents of COM20022I Internal Memory upon writing Address Pointer low only once. The SWAP bit is used to swap the upper and lower data byte. The SWAP bit is located at bit 0 of ADDRESS PTR_LOW register. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit.
6.2.3
Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator interaction with the network. The node determines the existence of other nodes by placing a Node ID value in the Tentative ID Register and waiting to see if the Tentative ID bit of the Diagnostic Status Register gets set. The network map developed by this method is only valid for a short period of time, since nodes may join or depart from the network at any time. When using the Tentative ID feature, a node cannot detect the existence of the next logical node to which it passes the token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the value 0000 0000 upon hardware reset only.
6.2.4
Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please refer to the Configuration Register and SUB ADR Register). The Node ID Register contains the unique value which identifies this particular node. Each node on the network must have a unique Node ID value at all times. The Duplicate ID bit of the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20022I does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID Register, the core wakes up but will not join the network until the TXEN bit of the Configuration Register is set. While the Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user with useful information about the network. The Node ID Register defaults to the value 0000 0000 upon hardware reset only.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
6.2.5
Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up accordingly (please refer to the Configuration Register and SUB ADR Register). The Next ID Register holds the value of the Node ID to which the COM20022I will pass the token. When used in conjunction with the Tentative ID Register, the Next ID Register can provide a complete network map. The Next ID Register is updated each time a node enters/leaves the network or when a network reconfiguration occurs. Each time the microsequencer updates the Next ID Register, a New Next ID interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or software reset.
6.2.6
Status Register
The COM20022I Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20022I, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register. The Status Register contents are defined as in Table 6.3, but are defined differently during the Command Chaining operation. Please refer to the Command Chaining section for the definition of the Status Register during Command Chaining operation. The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset.
6.2.7
Diagnostic Status Register
The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node operation. Various combinations of these bits and the TXEN bit of the Configuration Register represent different situations. All of these bits, except the Excessive NAcK bit and the New Next ID bit, are reset to logic "0" upon reading the Diagnostic Status Register or upon software or hardware reset. The EXCNAK bit is reset by the "POR Clear Flags" command or upon software or hardware reset. The Diagnostic Status Register defaults to the value 0000 000X upon either hardware or software reset.
6.2.8
Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any combinations of written data other than those listed in Table 6.5 are not permitted and may result in incorrect chip and/or network operation.
6.2.9
Address Pointer Registers
These read/write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer addresses should be written by first writing to the High Register and then writing to the Low Register because writing to the Low Register loads the address. The contents of the Address Pointer High and Low Registers are undefined upon hardware reset. Writing to Address Pointer low loads the address. The DMAEN bit (new to the COM20022I) is located at bit 3 of the ADDRESS PTR HIGH register. The DMAEN bit is used to Disable/Enable the assertion of the DMA Request (DREQ pin) after writing the Address Pointer Low register. The SWAP bit (new to the COM20022I) is located at bit 0 of Address Pointer Low register. The SWAP bit is used to swap the upper and lower data byte. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
6.2.10 Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the COM20022I. The Configuration Register defaults to the value 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to the selection in Register 7.
6.2.11 Sub-Address Register
The sub-address register is new to the COM20022I, previously a reserved register. Bits 2, 1 and 0 are used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0. They are exactly same as those in the Configuration register. If the SUBAD1 and SUBAD0 bits in the Configuration register are changed, the SUBAD1and SUBAD0 in the Sub-Address register are also changed. SUBAD2 is a new subaddress bit. It Is used to access the 3 new Set Up registers, SETUP2, BUS CONTROL and DMA COUNT. These registers are selected by setting SUBAD2=1. The SUBAD2 bit is cleared automatically by writing the Configuration register. Write Bits[7:3] to `0' for proper operation.
6.2.12 Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the bit definitions of the Configuration Register). The Setup 1 Register allows the user to change the network speed (data rate) or the arbitration speed independently, invoke the Receive All feature and change the nPULSE1 driver type. The data rate may be slowed to 156.25Kbps and/or the arbitration speed may be slowed by a factor of two. The Setup 1 Register defaults to the value 0000 0000 upon hardware reset only.
6.2.13 Setup 2 Register
The Setup 2 Register is new to the COM20022I. It is an 8-bit read/write register accessed when the Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This register contains bits for various functions. The CKUP1,0 bits select the clock to be generated from the 20 MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new timing for certain functions in the COM20022I (if EF = 0, the timing is the same as in the COM20020 Rev. B). See Appendix "A". The NOSYNC bit is used to enable the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM initialization sequence to be written. If set, the line does not have to be idle for the initialization sequence to be written. See Appendix "A". The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for shorter time periods has the benefit of shortened network reconfiguration periods. The time periods shown in the table on the following page are limited by a maximum number of nodes in the network. These timeout period values are for 10Mbps. For other data rates, scale the time-out period time values accordingly; the maximum node count remains the same.
RCNTM1 0 0 1 1 Note 6.1 RCNTM0 0 1 0 1 TIME-OUT PERIOD 210 mS 52.5 mS 26.25 mS 13.125 mS* MAX NODE COUNT Up to 255 nodes Up to 64 nodes Up to 32 nodes Up to 16 nodes (Note 6.1)
The node ID value 255 must exist in the network for the 13.125 mS time-out to be valid.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
6.3
Bus Control Register
The Bus Control Register is new to the COM20022I. It is an 8-bit read/write register accessed when the Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This register contains bits for control of the DMA functionality. The DRQPOL bit is used to set the active polarity of the DREQ pin. The TCPOL bit is used to set the active polarity of TC pin. The DMAMD[0,1] bits select the data transfer mode of the DMA, either non-burst, burst, ProgrammableBurst by timer or programmable burst by cycle counter. This transfer mode influences to the timing the DREQ pin. The use of the ITCEN/RTRG bit transfer mode dependent. ITCEN is the Internal Terminal Counter Enable. It is used to select whether the DMA is terminated by external TC or by either internal or external TC. ITCEN is for Non-Burst or Burst mode. RTRG selects the re-trigger mode as either external or internal. It is for the two Programmable-Burst modes. If RTRG = 0, the deasserted DREQ pin is reasserted on the falling edge of the nREFEX pin. If RTRG = 1, the deasserted DREQ pin is reasserted by the timeout of the internal timer (350 ns or 750 ns, as selected by the GTTM bit.) See Figure below.
RTRG=0 RTRG=1 350/750ns nREFEX DREQ nDACK nWR/nRD DREQ nDACK nWR/nRD
Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing
The use of the TC8/RSYN/GTTM bit is also transfer mode dependent. TC8 is bit 8 of the Terminal Count register. RSYN is the refresh synchronous bit; it is used to select whether the DMA is started immediately or after Refresh execution. GTTM is the Gate Time bit; it is used to select the gate time of the Programmable-Burst transfer. TC8 is for Non-Burst or Burst mode. RSYN and GTTM are for the two Programmable-Burst modes. The W16 bit is used to enable/disable the 16 bit access.
6.4
DMA Count Register
The DMA COUNT Register is new to the COM20022I. It is an 8-bit read/write register accessed when the Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This register contains bits for control of the DMA functionality. The TC7-TC0 /TIM7-TIM0 /CYC7-CYC0 bits have one of three functions depending on the DMA transfer mode. TC7-TC0 are for Non-Burst or Burst mode. These are the lower 8 bits of the Terminal Count setting register (the MSB is in the Bus Control Register). The TIM7-TIM0 bits are for setting the time of the continuous DMA transfer in Programmable-Burst by Timer mode. The CYC7-CYC0 bits are for setting the cycle count value of the continuous DMA transfer in Programmable-Burst by cycle mode.
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Table 6.3 - Status Register BIT 7 BIT NAME Receiver Inhibited SYMBOL RI DESCRIPTION This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued, or a packet has been deposited into the RAM buffer page fnn as specified by the last "Enable Receive to Page fnn" command. No messages will be received until this command is issued, and once the message has been received, the RI bit is set, thereby inhibiting the receiver. The RI bit is cleared by issuing an "Enable Receive to Page fnn" command. This bit, when set, will cause an interrupt if the corresponding bit of the Interrupt Mask Register (IMR) is also set. When this bit is set and another station attempts to send a packet to this station, this station will send a NAK. These bits are undefined. This bit, if high, indicates that the COM20022I has been reset by either a software reset, a hardware reset, or writing 00H to the Node ID Register. The POR bit is cleared by the "Clear Flags" command. This bit is intended for test and diagnostic purposes. It is a logic "0" under normal operating conditions. This bit, if high, indicates that the Line Idle Timer has timed out because the RXIN pin was idle for 20.5S. The RECON bit is cleared during a "Clear Flags" command. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. The interrupt service routine should consist of examining the MYRECON bit of the Diagnostic Status Register to determine whether there are consecutive reconfigurations caused by this node. This bit, if high, indicates that the packet transmitted as a result of an "Enable Transmit from Page fnn" command has been acknowledged. This bit should only be considered valid after the TA bit (bit 0) is set. Broadcast messages are never acknowledged. The TMA bit is cleared by issuing the "Enable Transmit from Page fnn" command. This bit, if high, indicates that the transmitter is available for transmitting. This bit is set when the last byte of scheduled packet has been transmitted out, or upon execution of a "Disable Transmitter" command. The TA bit is cleared by issuing the "Enable Transmit from Page fnn" command after the node next receives the token. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set.
6,5 4
(Reserved) Power On Reset
POR
3 2
Test Reconfiguration
TEST RECON
1
Transmitter Message Acknowledged Transmitter Available
TMA
0
TA
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Table 6.4 - Diagnostic Status Register BIT 7 BIT NAME SYMBOL My Reconfiguration MYRECON DESCRIPTION This bit, if high, indicates that a past reconfiguration was caused by this node. It is set when the Lost Token Timer times out, and should be typically read following an interrupt caused by RECON. Refer to the Improved Diagnostics section for further detail. This bit, if high, indicates that the value in the Node ID Register matches both Destination ID characters of the token and a response to this token has occurred. Trailing zero's are also verified. A logic "1" on this bit indicates a duplicate Node ID, thus the user should write a new value into the Node ID Register. This bit is only useful for duplicate ID detection when the device is off line, that is, when the transmitter is disabled. When the device is on line this bit will be set every time the device gets the token. This bit is reset automatically upon reading the Diagnostic Status Register. Refer to the Improved Diagnostics section for further detail. This bit, if high, indicates that data activity (logic "1") was detected on the RXIN pin of the device. Refer to the Improved Diagnostics section for further detail. This bit, if high, indicates that a token has been seen on the network, sent by a node other than this one. Refer to the Improved Diagnostic section for further detail. This bit, if high, indicates that either 128 or 4 Negative Acknowledgements have occurred in response to the Free Buffer Enquiry. This bit is cleared upon the "POR Clear Flags" command. Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. Refer to the Improved Diagnostics section for further detail. This bit, if high, indicates that a response to a token whose DID matches the value in the Tentative ID Register has occurred. The second DID and the trailing zero's are not checked. Since each node sees every token passed around the network, this feature can be used with the device online in order to build and update a network map. Refer to the Improved Diagnostics section for further detail. This bit, if high, indicates that the Next ID Register has been updated and that a node has either joined or left the network. Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. The bit is cleared by reading the Next ID Register. These bits are undefined.
6
Duplicate ID
DUPID
5
Receive Activity Token Seen
RCVACT
4
TOKEN
3
Excessive NAK
EXCNAK
2
Tentative ID
TENTID
1
New Next ID
NEW NXTID
1,0
(Reserved)
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Table 6.5 - Command Register DATA 0000 0000 COMMAND Clear Transmit Interrupt Disable Transmitter DESCRIPTION This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command.
0000 0001
0000 0010
Disable Receiver
b0fn n100
Enable Receive to Page fnn
00fn n011
Enable Transmit from Page fnn
0000 c101
Define Configuration Clear Flags
000r p110
0000 1000
0001 1000 0001 0000
Clear Receive Interrupt Start Internal Operation Clear Mask bit of DMAEND
This command will cancel any pending transmit command (transmission that has not yet started) and will set the TA (Transmitter Available) status bit to logic "1" when the COM20022I next receives the token. This command will cancel any pending receive command. If the COM20022I is not yet receiving a packet, the RI (Receiver Inhibited) bit will be set to logic "1" the next time the token is received. If packet reception is already underway, reception will run to its normal conclusion. This command allows the COM20022I to receive data packets into RAM buffer page fnn and resets the RI status bit to logic "0". The values placed in the "nn" bits indicate the page that the data will be received into (page 0, 1, 2, or 3). If the value of "f" is a logic "1", an offset of 256 bytes will be added to that page specified in "nn", allowing a finer resolution of the buffer. Refer to the Selecting RAM Page Size section for further detail. If the value of "b" is logic "1", the device will also receive broadcasts (transmissions to ID zero). The RI status bit is set to logic "1" upon successful reception of a message. This command prepares the COM20022I to begin a transmit sequence from RAM buffer page fnn the next time it receives the token. The values of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3). If "f" is logic "1", an offset of 256 bytes is the start of the page specified in "nn", allowing a finer resolution of the buffer. Refer to the Selecting RAM Page Size section for further detail. When this command is loaded, the TA and TMA bits are reset to logic "0". The TA bit is set to logic "1" upon completion of the transmit sequence. The TMA bit will have been set by this time if the device has received an ACK from the destination node. The ACK is strictly hardware level, sent by the receiving node before its microcontroller is even aware of message reception. Refer to Figure 3.1 for details of the transmit sequence and its relation to the TA and TMA status bits. This command defines the maximum length of packets that may be handled by the device. If "c" is a logic "1", the device handles both long and short packets. If "c" is a logic "0", the device handles only short packets. This command resets certain status bits of the COM20022I. A logic "1" on "p" resets the POR status bit and the EXCNAK Diagnostic status bit. A logic "1" on "r" resets the RECON status bit. This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command. This command restarts the stopped internal operation after changing CKUP1 or CKUP0 bit. This command resets a mask bit of the DMAEND. It is for clearing interrupt by DMA transfer finished.
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Table 6.6 - Address Pointer High Register BIT 7 BIT NAME Read Data SYMBOL RDDATA DESCRIPTION This bit tells the COM20022I whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. This bit controls whether the address pointer will increment automatically. A logic "1" on this bit allows automatic increment of the pointer after each access, while a logic "0" disables this function. Please refer to the Sequential Access Memory section for further detail. These bits are undefined. This bit is used to Disable/Enable the assertion of the DMA Request (DREQ pin) after writing the Address Pointer Low register. DMAEN=0: Disable (Default). DMAEN=1: Enable the assertion of the DREQ pin after writing the Address Pointer Low register. Writing DMAEN=0 during the DMA operation will negate the DREQ pin immediately. The DMA operation is terminated immediately after the next DACK pin negation. The inverting signal of DAMEN is the Interrupt source signal DMAEND. The DMAEN bit is cleared automatically by finishing the DMA. If the DMAEND bit in the Mask register is not masked, the Interrupt occurs by finishing the DMA operation. These bits hold the upper three address bits which provide addresses to RAM.
6
Auto Increment
AUTOINC
5-4 3
(Reserved) DMA Enable
DMAEN
2-0
Address 10-8
A10-A8
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Table 6.7 - Address Pointer Low Register BIT 7-0 BIT NAME Address 7-0 SYMBOL A7-A0 DESCRIPTION These bits hold the lower 8 address bits which provide the addresses to RAM. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit. Swap bit is undefined after a hardware reset. The swap bit must be set before W16 bit is set to "1". The swap bit is used to swap the upper and lower data byte. The swap bit influences both CPU cycle and DMA cycle. See Table Below. Swap Bit D7-D0 Pin Detected Host Interface D15-D8 Mode Pin Intel 80xx Mode 0 Odd Even
SWAP
(RD, WR Mode) Motorola 68xx Mode (DIR, DS Mode)
1 0 1
Even Even Odd
Odd Odd Even
Table 6.8 - Sub Address Register BIT 7-3 2,1,0 BIT NAME Reserved Sub Address 2,1,0 SYMBOL DESCRIPTION These bits are undefined. These bits determine which register at address 07 may be accessed. The combinations are as follows:
SUBAD 2,1,0
SUBAD1 SUBAD0 Register SUBAD2 0 0 0 Tentative ID \ (Same 0 0 1 Node ID \ as in 0 1 0 Setup 1 / Config 0 1 1 Next ID / Register) 1 0 0 Setup 2 1 0 1 Bus Control 1 1 0 DMA Count 1 1 1 Reserved SUBAD1 and SUBAD0 are exactly the same as exist in the Configuration Register. SUBAD2 is cleared automatically by writing the Configuration Register.
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Table 6.9 - Configuration Register BIT 7 BIT NAME
Reset
SYMBOL RESET
6
Command Chaining Enable Transmit Enable
CCHEN
5
TXEN
4,3
Extended Timeout 1,2
ET1, ET2
DESCRIPTION A software reset of the COM20022I is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. This bit must be brought back to logic "0" to release the reset. This bit, if high, enables the Command Chaining operation of the device. Please refer to the Command Chaining section for further details. A low level on this bit ensures software compatibility with previous SMSC ARCNET devices. When low, this bit disables transmissions by keeping nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive. When high, it enables the above signals to be activated during transmissions. This bit defaults low upon reset. This bit is typically enabled once the Node ID is determined, and never disabled during normal operation. Please refer to the Improved Diagnostics section for details on evaluating network activity. These bits allow the network to operate over longer distances than the default maximum 1 mile by controlling the Response, Idle, and Reconfiguration Times. All nodes should be configured with the same timeout values for proper network operation. For the COM20022I with a 20 MHz crystal oscillator, the bit combinations follow: Reconfig Idle Time Time Response ET2 (mS) ET1 (S) Time (S) 0 0 420 298.4 328 0 1 420 149.2 164 1 0 420 74.7 82 1 1 210 18.7 20.5 Note: These values are for 10Mbps and RCNTMR[1,0]=00. Reconfiguration time is changed by the RCNTMR1 and RCNTMR0 bits.
2
Backplane
BACKPLANE SUBAD 1,0
A logic "1" on this bit puts the device into Backplane Mode signaling which is used for Open Drain and Differential Driver interfaces. These bits determine which register at address 07 may be accessed. The combinations are as follows: SUBAD0 Register SUBAD1 0 0 Tentative ID 0 1 Node ID 1 0 Setup 1 1 1 Next ID See also the Sub Address Register.
1,0
Sub Address 1,0
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Table 6.10 - Setup 1 Register BIT 7 BIT NAME Pulse1 Mode SYMBOL P1MODE DESCRIPTION This bit determines the type of PULSE1 output driver used in Backplane Mode. When high, a push/pull output is used. When low, an open drain output is used. The default is open drain. This bit, when set, will cause the EXNACK bit in the Diagnostic Status Register to set after four NACKs to Free Buffer Enquiry are detected by the COM20022I. This bit, when reset, will set the EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default is 128. Do not set. This bit, when set, allows the COM20022I to receive all valid data packets on the network, regardless of their destination ID. This mode can be used to implement a network monitor with the transmitter on- or off-line. Note that ACKs are only sent for packets received with a destination ID equal to the COM20022I's programmed node ID. This feature can be used to put the COM20022I in a 'listen-only' mode, where the transmitter is disabled and the COM20022I is not passing tokens. Defaults low. These bits are used to determine the data rate of the COM20022I. The following table is for a 20 MHz crystal: (Clock Multiplier is bypassed) CKP3 CKP2 CKP1 DIVISOR SPEED 0 0 0 8 2.5Mbs 0 0 1 16 1.25Mbs 0 1 0 32 625Kbs 0 1 1 64 312.5Kbs 1 0 0 128 156.25Kbs Note: The lowest data rate achievable by the COM20022I is 156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multiplier output clock speed greater than 20 MHz, CKP3, CKP2 and CKP1 must all be zero.
6
Four NACKS
FOUR NACKS
5 4
Reserved Receive All
RCVALL
3,2,1
Clock Prescaler Bits 3,2,1
CKP3,2,1
0
Slow Arbitration Select
SLOWARB
This bit, when set, will divide the arbitration clock by 2. Memory cycle times will increase when slow arbitration is selected.
Note: For clock multiplier output clock speeds greater than 40 MHz, SLOWARB must be set. Defaults to low.
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Table 6.11 - Setup 2 Register BIT 7 BIT NAME Read Bus Timing Select SYMBOL RBUSTMG DESCRIPTION This bit is used to Disable/Enable the High Speed CPU Read function for High Speed CPU bus support. RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. That is, if BUSTMG (pin 26) = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled. It does not influence write operation. High speed CPU Read operation is only for non-multiplexed bus. This bit is undefined. Higher frequency clocks are generated from the 20 MHz crystal through the selection of these two bits as shown. This clock multiplier is powered-down on default. After changing the CKUP1 and CKUP0 bits, the ARCNET core operation is stopped and the internal PLL in the clock multiplier is awakened and it starts to generate the 40 MHz. The lock out time of the internal PLL is 8Sec typically. After 1 mS it is necessary to write command data '18H' to command register for re-starting the ARCNET core operation. EF bit must be `1' if the data rate is over 5Mbps. CAUTION: Changing the CKUP1 and CKUP0 bits must be one time or less after releasing a hardware reset.
6 5,4
Reserved Clock Multiplier
CKUP1, 0
CKUP1 0 0 1 1
CKUP0 0 1 0 1
Clock Frequency (Data Rate) 20 MHz (Up to 2.5Mbps) Default 40 MHz (Up to 5Mbps) Reserved 80 MHz (Only 10Mbps)
Note: After changing the CKUP1 or CKUP0 bits, it is necessary to write a command data '18H' to the command register. Because after changing the CKUP [1, 0] bits, the internal operation is stopped temporarily. The writing of the command is to start the operation.
These initializing steps are shown below. 1. Hardware reset (Power ON) 2. 3. 4. 5. 3 Enhanced Functions EF Change CKUP[1, 0] bit Wait 1mSec (wait until stable oscillation) Write command '18H' (start internal operation) Start initializing routine (Execute existing software)
2
No Synchronous
NOSYNC
This bit is used to enable the new enhanced functions in the COM20022I. EF = 0: Disable (Default), EF = 1: Enable. If EF = 0, the timing and function is the same as in the COM20020, Revision B. See appendix "A". EF bit must be `1' if the data rate is over 5Mbps. EF bit should be `1' for new design customers. EF bit should be `0' for replacement customers. This bit is used to enable the SYNC command during initialization. NOSYNC= 0, Enable (Default) The line must be idle for the RAM initialization sequence to be written. NOSYNC= 1, Disable:) The line does not have to be idle for the RAM initialization sequence to be written. See appendix "A".
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BIT 1,0
BIT NAME Reconfiguration Timer 1, 0
SYMBOL RCNTM1,0
DESCRIPTION These bits are used to program the reconfiguration timer as a function of maximum node count. These bits set the time out period of the reconfiguration timer as shown below. The time out periods shown are for 10 Mbps. RCNTM1 RCNTM0 Time Out Period Max Node Count 0 0 210 mS Up to 255 nodes 0 1 52.5 mS Up to 64 nodes 1 0 26.25 mS Up to 32 nodes 1 1 13.125 mS* Up to 16 nodes Note*: The node ID value 255 must exist in the network for 13.125 mS timeout to be valid.
Table 6.12 - Bus Control Register BIT 7 BIT NAME 16 Bit Access SYMBOL W16 DESCRIPTION This bit is used to Disable/Enable the 16 bit access. It influences both CPU cycle and DMA cycle. W16= 0: Disable (Default); W16= 1: Enable This bit is undefined. The function of this bit is mode dependent. ITCEN is for Non-Burst or Burst mode. RTRG is for the two Programmable-Burst modes. ITCEN = 0: Terminate the DMA only by External TC. ITCEN = 1: Terminate the DMA by Internal or External TC. RTRG = 0: External Re-Trigger mode; Negated DREQ pin is Reasserted by falling edge of nREFEX pin. RTRG = 1: Internal ReTrigger mode; Negated DREQ pin is Re-asserted by timeout of internal gate timer (350ns/750ns). The function of this bit is mode dependent. TC8 is for Non-burst or burst mode. RSYN and GTTM are for the two Programmable-Burst modes. RSYN is for External Re-Trigger mode. GTTM is for internal Re-Trigger mode. Non-burst or burst mode: TC8: Bit 8 (MSB) of 9 bit Terminal Count setting register. The other 8 bits are in the DMA Count register. Terminal Count setting register is ignored when ITCEN = 0. Programmable-Burst and External Re-Trigger mode: RSYN = 0: DMA is started Immediately. RSYN = 1: DMA is started after Refresh execution. Programmable-Burst and Internal Re-Trigger mode: GTTM = 0: Gate Time is 350nS (min) GTTM = 1: Gate Time is 750nS (min) These bits select the data transfer mode of the DMA. These transfer modes influence the timing of asserting/negating the DREQ pin. DMAMD1 DMAMD0 Transfer Mode 0 0 Non-Burst (Default) 0 1 Burst 1 0 Programmable-Burst by Timer 1 1 Programmable-Burst by Cycle Counter This bit sets the Active polarity of TC pin. TCPOL = 0: Active High (Default), TCPOL = 1 Active Low This bit sets the Active polarity of DREQ pin. DRQPOL = 0: Active High (Default), DRQPOL = 1 Active Low
6 5
Reserved Internal Terminal Counter Enable; Re-Trigger mode
ITCEN/ RTRG
4
Terminal Count Bit 8 Refresh Synchronous Gate Time
TC8/ RSYN/ GTTM
3,2
DMA Transfer Mode
DMAMD1,D MAMD0
1 0
TC Polarity DREQ Polarity
TCPOL DRQPOL
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Table 6.13 - DMA Count Register BIT 7-0 BIT NAME Terminal Count SYMBOL TC7-TC0 DESCRIPTION TC7-TC0: Used for non-burst or burst mode. These are the lower 8 bits of the Terminal Count setting register. The MSB (TC8) is in the Bus Control Register. The Terminal Count setting range is from 1 to 512 counts (TC8 - TC0 all zeroes means 512 counts). TIM7-TIM0: Used for Programmable-Burst by Timer mode. These bits are for setting the term of the continuous DMA transfer. The time range is from 100nS to 25.6S. The step is 100nS (TIM7-TIM0 all zeroes means 25.6s). CYC7-CYC0: Used for Programmable-Burst by Cycle mode. These bits are for setting the term of the continuous DMA transfer. The cycle range is from 2 to 256 cycles. CYC7-CYC0 all zeroes means 256 cycles. (1 is illegal)
Timer Mode
TIM7-TIM0
Cycle Mode
CYC7-CYC0
Data Register I/O Address 04H Memory Data Bus 8 2K x 8 INTERNAL RAM
D0-D7 Address Pointer Register I/O Address 02H High I/O Address 03H Low
Memory Address Bus 11-Bit Counter 11
Figure 6.2 - Sequential Access Operation
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6.5
Internal RAM
The integration of the 2K x 8 RAM in the COM20022I represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM. The integration of RAM represents significant cost savings because it isolates the system designer from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs, and layout complexity.
6.5.1
Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory, the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is channeled to and from the microcontroller via the 8-bit data register. For example: a packet in the internal RAM buffer is read by the microcontroller by writing the corresponding address into the Address Pointer High and Low Registers (offsets 02H and 03H). Note that the High Register should be written first, followed by the Low Register, because writing to the Low Register loads the address. At this point the device accesses that location and places the corresponding data into the data register. The microcontroller then reads the data register (offset 04H) to obtain the data at the specified location. If the Auto Increment bit is set to logic "1", the device will automatically increment the address and place the next byte of data into the data register, again to be read by the microcontroller. This process is continued until the entire packet is read out of RAM. Refer to Figure 5.6 for an illustration of the Sequential Access operation. When switching between reads and writes, the pointer must first be written with the starting address. At least one cycle time should separate the pointer being loaded and the first read (see timing parameters).
6.5.2
Access Speed
The COM20022I is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to memory. For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the Setup1 Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by two, the duty cycle of the input clock may be relaxed.
6.6
Software Interface
The microcontroller interfaces to the COM20022I via software by accessing the various registers. These actions are described in the Internal Registers section. The software flow for accessing the data buffer is based on the Sequential Access scheme. The basic sequence is as follows: Disable Interrupts Write to Pointer Register High (specifying Auto-Increment mode) Write to Pointer Register Low (this loads the address) Enable Interrupts Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer) The pointer may now be read to determine how many transfers were completed.
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The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to the initialization sequence and the maintenance of the network map. Additionally, it is necessary to understand the details of how the other Internal Registers are used in the transmit and receive sequences and to know how the internal RAM buffer is properly set up. The sequence of events that tie these actions together is discussed as follows.
6.6.1
Selecting RAM Page Size
During normal operation, the 2K x 8 of RAM is divided into four pages of 512 bytes each. The page to be used is specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies page 0, 1, 2, or 3. This allows the user to have constant control over the allocation of RAM. When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set to logic "1", an offset of 256 bytes is added to the page specified. For example: to transmit from the second half of page 0, the command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the Command Register. This allows a finer resolution of the buffer pages without affecting software compatibility. This scheme is useful for applications which frequently use packet sizes of 256 bytes or less, especially for microcontroller systems with limited memory capacity. The remaining portions of the buffer pages which are not allocated for current transmit or receive packets may be used as temporary storage for previous network data, packets to be sent later, or as extra memory for the system, which may be indirectly accessed. If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. In this case, the transmit pages may be made 256 bytes long, leaving at least 512 bytes free at any given time. Even if the Command Chaining operation is being used, 512 bytes is still guaranteed to be free because Command Chaining only requires two pages for transmit and two for receive (in this case, two 256 byte pages for transmit and two 512 byte pages for receive, leaving 512 bytes free). Please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. The COM20022I does not check page boundaries during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time. Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K free). The general rule which may be applied to determine where in RAM a page begins is as follows: Address = (nn x 512) + (f x 256).
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ADDRESS 0 1 2
SHORT PACKET FORMAT SID DID COUNT = 256-N NOT USED
ADDRESS 0 1 2 3
LONG PACKET FORMAT SID DID 0 COUNT = 512-N NOT USED
COUNT
DATA BYTE 1 DATA BYTE 2 COUNT DATA BYTE N-1
DATA BYTE 1 DATA BYTE 2
255 511
DATA BYTE N NOT USED 511 DATA BYTE N-1 DATA BYTE N
N = DATA PACKET LENGTH SID = SOURCE ID DID = DESTINATION ID (DID = 0 FOR BROADCASTS)
Figure 6.3 - RAM Buffer Packet Configuration
6.6.2
Transmit Sequence
During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long packets are enabled, the COM20022I interprets the packet as either a long or short packet, depending on whether the buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in Figure 5.7 Address 0 contains the Source Identifier (SID); Address 1 contains the Destination Identifier (DID); Address 2 (COUNT) contains, for short packets, the value 256-N, where N represents the number of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the number of information bytes in the message. The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20022I puts the local ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes. A minimum value of 257 exists on a long packet so that the COUNT is expressible in eight bits. This leaves three exception packet lengths which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of these lengths must be sent, the user must add dummy bytes to the packet in order to make the packet fit into a long packet. Once the packet is written into the buffer, the microcontroller awaits a logic "1" on the TA bit, indicating that a previous transmit command has concluded and another may be issued. Each time the message is loaded and a transmit command issued, it will take a variable amount of time before the message is transmitted, depending on the traffic on the network and the location of the token at the time the transmit command was issued. The conclusion of the Transmit Command will generate an interrupt if the Interrupt Mask allows it. If the device is configured for the Command Chaining operation, please see the Command Chaining section for further detail on the transmit sequence. Once the TA bit becomes a logic "1", the microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the
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message is not a BROADCAST, the COM20022I automatically sends a FREE BUFFER ENQUIRY to the destination node in order to send the message. At this point, one of four possibilities may occur. The first possibility is if a free buffer is available at the destination node, in which case it responds with an ACKnowledgement. At this point, the COM20022I fetches the data from the Transmit Buffer and performs the transmit sequence. If a successful transmit sequence is completed, the TMA bit and the TA bit are set to logic "1". If the packet was not transmitted successfully, TMA will not be set. A successful transmission occurs when the receiving node responds to the packet with an ACK. An unsuccessful transmission occurs when the receiving node does not respond to the packet. The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative AcKnowledgement. A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the token is passed on from the transmitting node to the next node. The next time the transmitter receives the token, it will again transmit a FREE BUFFER ENQUIRY. If a NAK is again received, the token is again passed onto the next node. The Excessive NAK bit of the Diagnostic Status Register is used to prevent an endless sending of FBE's and NAK's. If no limit of FBE-NAK sequences existed, the transmitting node would continue issuing a Free Buffer Enquiry, even though it would continuously receive a NAK as a response. The EXCNAK bit generates an interrupt (if enabled) in order to tell the microcontroller to disable the transmitter via the "Disable Transmitter" command. This causes the transmission to be abandoned and the TA bit to be set to a logic "1" when the node next receives the token, while the TMA bit remains at a logic "0". Please refer to the Improved Diagnostics section for further detail on the EXCNAK bit. The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node does not respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0". The user should determine whether the node should try to reissue the transmit command. The fourth possibility is if a non-traditional response is received (some pattern other than ACK or NAK, such as noise). In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the next node to time out, thus generating a network reconfiguration. The "Disable Transmitter" command may be used to cancel any pending transmit command when the COM20022I next receives the token. Normally, in an active network, this command will set the TA status bit to a logic "1" when the token is received. If the "Disable Transmitter" command does not cause the TA bit to be set in the time it takes the token to make a round trip through the network, one of three situations exists. Either the node is disconnected from the network, or there are no other nodes on the network, or the external receive circuitry has failed. These situations can be determined by either using the improved diagnostic features of the COM20022I or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message.
6.6.3
Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous reception has concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt Mask Register is set to logic "1". Otherwise, the microcontroller must periodically check the Status Register. Once the microcontroller is alerted to the fact that the previous reception has concluded, it may issue the "Enable Receive to Page fnn" command, which resets the RI bit to logic "0" and selects a new page in the RAM buffer. Again, the appropriate buffer size is specified in the "Define Configuration" command. Typically, the page which just received the data packet will be read by the microcontroller at this point. Once the "Enable Receive to Page fnn" command is issued, the microcontroller attends to other duties. There is no way of knowing how long the new reception will take, since another node may transmit a packet at any time. When another node does transmit a packet to this node, and if the "Define Configuration" command has enabled the reception of long packets, the COM20022I interprets the packet as either a long or short packet, depending on whether the content of the buffer location 2 is zero or non-zero. The format of the buffer is shown in Figure 5.7. Address 0 contains the Source Identifier (SID), Address 1 contains the Destination Identifier (DID), and Address 2 contains, for short packets, the value 256-N, where N represents the message length, or for long packets, the value 0, indicating that it is indeed a long packet. In the latter case, Address 3 contains the value 512-N, where N represents the message length. Note that on reception,
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the COM20022I deposits packets into the RAM buffer in the same format that the transmitting node arranges them, which allows for a message to be received and then retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20022I sets the RI bit to logic "1" to signal the microcontroller that the reception is complete.
MSB
LSB
TRI
RI
TA
POR
TEST
RECON
TMA
TTA
TRI
TMA
TTA
Figure 6.4 - Command Chaining Status Register Queue
6.7
Command Chaining
The Command Chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention. Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20022I to be compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic "1" on bit 6 of the Configuration Register. In Command Chaining, the Status Register appears as in Figure 6.4. The following is a list of Command Chaining guidelines for the software programmer. Further detail can be found in the Transmit Command Chaining and Receive Command Chaining sections. The device is designed such that the interrupt service routine latency does not affect performance. Up to two outstanding transmissions and two outstanding receptions can be pending at any given time. The commands may be given in any order. Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the device, along with their respective status bits. The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations and TRI (Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion of a packet transmission only. TRI is set upon completion of a packet reception only. Typically there is no need to mask the TTA and TRI bits after clearing the interrupt. The traditional TA and RI bits are still available to reflect the present status of the device.
6.7.1
Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20022I responds in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for the device in the Command Chaining mode. In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a second "Enable Transmit from Page fnn" command. The COM20022I stores the fact that the second transmit command was issued, along with the page number.
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After the first transmission is completed, the COM20022I updates the Status Register by setting the TTA bit, which generates an interrupt. The interrupt service routine should read the Status Register. At this point, the TTA bit will be found to be a logic "1" and the TMA (Transmit Message Acknowledge) bit will tell the processor whether the transmission was successful. After reading the Status Register, the "Clear Transmit Interrupt" command is issued, thus resetting the TTA bit and clearing the interrupt. Note that only the "Clear Transmit Interrupt" command will clear the TTA bit and the interrupt. It is not necessary, however, to clear the bit or the interrupt right away because the status of the transmit operation is double buffered in order to retain the results of the first transmission for analysis by the processor. This information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note that the interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is acknowledged. The COM20022I guarantees a minimum of 200nS (at EF=1) interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether the appropriate transmission was a success. The TMA bit should only be considered valid after the corresponding TTA bit has been set to a logic "1". The TMA bit never causes an interrupt. When the token is received again, the second transmission will be automatically initiated after the first is completed by using the stored "Enable Transmit from Page fnn" command. The operation is as if a new "Enable Transmit from Page fnn" command has just been issued. After the first Transmit status bits are cleared, the Status Register will again be updated with the results of the second transmission and a second interrupt resulting from the second transmission will occur. The COM20022I guarantees a minimum of 200ns (at EF=1) interrupt inactive time interval before the following edge. The Transmitter Available (TA) bit of the Interrupt Mask Register now masks only the TTA bit of the Status Register, not the TA bit as in the non-chaining mode. Since the TTA bit is only set upon transmission of a packet (not by RESET), and since the TTA bit may easily be reset by issuing a "Clear Transmit Interrupt" command, there is no need to use the TA bit of the Interrupt Mask Register to mask interrupts generated by the TTA bit of the Status Register. In Command Chaining mode, the "Disable Transmitter" command will cancel the oldest transmission. This permits canceling a packet destined for a node not ready to receive. If both packets should be canceled, two "Disable Transmitter" commands should be issued.
6.7.2
Receive Command Chaining
Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable Receive from Page fnn" commands. After the first packet is received into the first specified page, the TRI bit of the Status Register will be set to logic "1", causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the interrupt service routine will read the Status Register. At this point, the RI bit will be found to be a logic "1". After reading the Status Register, the "Clear Receive Interrupt" command should be issued, thus resetting the TRI bit and clearing the interrupt. Note that only the "Clear Receive Interrupt" command will clear the TRI bit and the interrupt. It is not necessary, however, to clear the bit or the interrupt right away because the status of the receive operation is double buffered in order to retain the results of the first reception for analysis by the processor, therefore the information will remain in the Status Register until the "Clear Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive Interrupt" command is issued, and the second interrupt will be stored until the first interrupt is acknowledged. A minimum of 200nS (at EF=1) interrupt inactive time interval between interrupts is guaranteed. The second reception will occur as soon as a second packet is sent to the node, as long as the second "Enable Receive to Page fnn" command was issued. The operation is as if a new "Enable Receive to Page fnn" command has just been issued. After the first Receive status bits are cleared, the Status Register will again be updated with the results of the second reception and a second interrupt resulting from the second reception will occur. In the COM20022I, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon
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reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a "Clear Receive Interrupt" command, there is no need to use the RI bit of the Interrupt Mask Register to mask interrupts generated by the TRI bit of the Status Register. In Command Chaining mode, the "Disable Receiver" command will cancel the oldest reception, unless the reception has already begun. If both receptions should be canceled, two "Disable Receiver" commands should be issued.
6.8
6.8.1
Reset Details
Internal Reset Logic
The COM20022I includes special reset circuitry to guarantee smooth operation during reset. Special care is taken to assure proper operation in a variety of systems and modes of operation. The COM20022I contains digital filter circuitry and a Schmitt Trigger on the nRESET signal to reject glitches in order to ensure fault-free operation. The COM20022I supports two reset options; software and hardware reset. A software reset is generated when a logic "1" is written to bit 7 of the Configuration Register. The device remains in reset as long as this bit is set. The software reset does not affect the microcontroller interface modes determined after hardware reset, nor does it affect the contents of the Address Pointer Registers, the Configuration Register, or the Setup1 Register. A hardware reset occurs when a low signal is asserted on the nRESET input. The minimum reset pulse width is 5TXTL. This pulse width is used by the internal digital filter, which filters short glitches to allow only valid resets to occur. Upon reset, the transmitter portion of the device is disabled and the internal registers assume those states outlined in the Internal Registers section. After the nRESET signal is removed the user may write to the internal registers. Since writing a non-zero value to the Node ID Register wakes up the COM20022I core, the Setup1 Register should be written before the Node ID Register. Once the Node ID Register is written to, the COM20022I reads the value and executes two write cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation.
6.9
6.9.1
Initialization Sequence
Bus Determination
Writing to and reading from an odd address location from the COM20022I's address space causes the COM20022I to determine the appropriate bus interface. When the COM20022I is powered on the internal registers may be written to. Since writing a non-zero value to the Node ID Register wakes up the core, the Setup1 Register should be written to before the Node ID Register. Until a non-zero value is placed into the NID Register, no microcode is executed, no tokens are passed by this node, and no reconfigurations are generated by this node. Once a non-zero value is placed in the register, the core wakes up, but the node will not attempt to join the network until the TX Enable bit of the Configuration Register is set. Before setting the TX Enable bit, the software may make some determinations. The software may first observe the Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health of the receiver and the network. Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable bit should still be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the Duplicate ID bit of the Diagnostic Status Register is set after a maximum of 210mS (or 420mS if the ET1 and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the COM20022I compares the value in the Node ID Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared.
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The user may then attempt a new ID value, wait 210mS before checking the Duplicate ID bit, and repeat the process until a unique Node ID is found. At this point, the TX Enable bit may be set to allow the node to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the MYRECON bit of the Diagnostic Status Register. The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the COM20022I has joined the network. Once a value is placed in the Tentative ID Register, the COM20022I looks for a response to a token whose DID matches the Tentative ID Register. The software can record this information and continue placing Tentative ID values into the register to continue building the network map. A complete network map is only valid until nodes are added to or deleted from the network. Note that a node cannot detect the existence of the next logical node on the network when using the Tentative ID. To determine the next logical node, the software should read the Next ID Register.
6.10
Improved Diagnostics
The COM20022I allows the user to better manage the operation of the network through the use of the internal Diagnostic Status Register. A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired, causing a reconfiguration by this node. After the Reconfiguration (RECON) bit of the Status Register interrupts the microcontroller, the interrupt service routine will typically read the MYRECON bit of the Diagnostic Status Register. Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be disabled so that the entire network is not held down while the node is being evaluated. The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with the same ID does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join the network. The Receive Activity (RCVACT) bit of the Diagnostic Status Register will be set to a logic "1" whenever activity (logic "1") is detected on the RXIN pin. The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network (except those tokens transmitted by this node). The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual events are occurring on the network, the user may find it valuable to use the TXEN bit of the Configuration Register to qualify events. Different combinations of the RCVACT, TOKEN, and TXEN bits, as shown indicate different situations:
6.10.1 Normal Results:
RCVACT=1, TOKEN=1, TXEN=0: The node is not part of the network. The network is operating properly without this node. RCVACT=1, TOKEN=1, TXEN=1: The node sees receive activity and sees the token. The basic transmit function is enabled. Network and node are operating properly. MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node network.
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6.10.2 Abnormal Results:
RCVACT=1, TOKEN=0, TXEN=X: The node sees receive activity, but does not see the token. Either no other nodes exist on the network, some type of data corruption exists, the media driver is malfunctioning, the topology is set up incorrectly, there is noise on the network, or a reconfiguration is occurring. RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled. The transmitter and/or receiver are not functioning properly. RCVACT=0, TOKEN=0, TXEN=0: No receive activity and basic transmit function disabled. This node is not connected to the network. The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in software. This function is necessary to limit the number of times a sender issues a FBE to a node with no available buffer. When the destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs, the EXCNAK bit of the sender is set, generating an interrupt. At this point the software may abandon the transmission via the "Disable Transmitter" command. This sets the TA bit to logic "1" when the node next receives the token, to allow a different transmission to occur. The timeout value for the EXNACK bit (128 or 4) is determined by the FOUR-NAKS bit on the Setup1 Register. The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the wraparound counter of the EXCNAK bit. When the EXCNAK bit goes high, indicating 128 or 4 NAKs, the "POR Clear Flags" command may be issued to reset the bit so that it will go high again after another count of 128 or 4. The software may count the number of times the EXCNAK bit goes high, and once the final count is reached, the "Disable Transmitter" command may be issued. The New Next ID bit permits the software to detect the withdrawal or addition of nodes to the network. The Tentative ID bit allows the user to build a network map of those nodes existing on the network. This feature is useful because it minimizes the need for human intervention. When a value placed in the Tentative ID Register matches the Node ID of another node on the network, the TENTID bit is set, telling the software that this NODE ID already exists on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated network map.
6.11
Oscillator
The COM20022I contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an oscillator. If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20022I contains an internal resistor. The crystal must have an accuracy of 0.020% or better. The oscillation frequency range is from 10 MHz to 20 MHz. The crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. The oscillation frequency must be 20MHz when the internal clock multiplier is turned on. The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other devices. The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390 pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected.
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Chapter 7
7.1
Operational Description
Maximum Guaranteed Ratings*
Operating Temperature Range ...............................................................................................-40oC to +85oC Storage Temperature Range ................................................................................................-55oC to +150oC Lead Temperature (soldering, 10 seconds) ....................................................................................... +325 oC Positive Voltage on any pin, with respect to ground ........................................................................VDD+0.3V Negative Voltage on any pin, with respect to ground ............................................................................. -0.3V Maximum VDD .......................................................................................................................................... +7V *Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied.
Note:
When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used.
7.2
DC Electrical Characteristics
VDD=5.0V10% COM20022I: TA=0oC to +70oC, COM20022II: TA=-40oC to +85oC
PARAMETER Low Input Voltage 1 (All inputs except A2, XTAL1, nRESET, nRD, nWR, nREFEX and RXIN) High Input Voltage 1 (All inputs except A2, XTAL1, nRESET, nRD, nWR, nREFEX and RXIN) Low Input Voltage 2 (XTAL1) High Input Voltage 2 (XTAL1)
SYMBOL VIL1
MIN
TYP
MAX 0.8
UNIT V
COMMENT TTL Levels
VIH1
2.0
V
TTL Levels
VIL2 VIH2 4.0
1.0
V V
TTL Clock Input
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PARAMETER Low to High Threshold Input Voltage (A2, nRESET, nRD, nWR, nREFEX and RXIN) High to Low Threshold Input Voltage (A2, nRESET, nRD, nWR, nREFEX and RXIN) Low Output Voltage 1 (nPULSE1 in Push/Pull Mode, nPULSE2, nTXEN, DREQ, nIOCS16) High Output Voltage 1 (nPULSE1 in Push/Pull Mode, nPULSE2, nTXEN, DREQ, nIOCS16) Low Output Voltage 2 (D0-D15) High Output Voltage 2 (D0-D15) Low Output Voltage 3 (nINTR) High Output Voltage 3 (nINTR) Low Output Voltage 4 (nPULSE1 in Open-Drain Mode) Dynamic VDD Supply Current
SYMBOL VILH
MIN
TYP 1.8
MAX
UNIT V
COMMENT Schmitt Trigger, All Values at VDD = 5V
VIHL
1.2
V
VOL1
0.4
V
ISINK=4mA
VOH1 VOH1C VOL2 VOH2 VOL3 VOH3 VOL4
2.4 0.8 x VDD 0.4 2.4 0.8 2.4 0.5
V
ISOURCE=-2mA ISOURCE=-200A (except DREQ, nIOCS16) ISINK=16mA ISOURCE=-12mA ISINK=24mA ISOURCE=-10mA ISINK=48mA Open Drain Driver 5 Mbps 10 Mbps All Outputs Open VIN=0.0V
V V V V V
IDD1 IDD2 IP 80
TBD TBD 200
mA mA
A
Input Pull-up Current (nPULSE1 in Open-Drain Mode, A1, AD0-AD2, D3-D15, nREFEX, (nDACK and TC in BUSTMG = H)) Input Leakage Current (All inputs except A1, AD0-AD2, D3-D15, XTAL1, XTAL2, nREFEX, (nDACK and TC in BUSTMG = H))
IL
10
A
VSS < VIN < VDD
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CAPACITANCE (TA = 25 C; fC = 1MHz; VDD = 0V)
Output and I/O pins capacitive load specified as follows:
PARAMETER Input Capacitance Output Capacitance 1 (All outputs except XTAL2, nPULSE1 in Push/Pull Mode) Output Capacitance 2 (nPULSE1, in BackPlane Mode Only - Open Drain) SYMBOL CIN COUT1 MIN TYP MAX 5.0 45 UNIT pF pF COMMENT
Maximum Capacitive Load which can be supported by each output.
COUT2
400
pF
AC Measurements are taken at the following points: Inputs: t t 2.4V 1.4V 0.4V t 2.4V 1.4V 0.4V 50% 0.8V t Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". 2.0V 50% 0.8V 2.0V Outputs:
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Chapter 8
AD0-AD2, D3-D15 nCS
Timing Diagrams
VALID t1 t2, t4 t3 t12 t6 t7 t14 Note 2 t10 Valid Value VALID DATA
ALE nDS
t11 t5
t13 t8
DIR nIOCS16 Previous Value
t15
t9 t16 Invalid
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low nDS Low to Valid Data nDS High to Data High Impedance Cycle Time (nDS Low to Next Time Low) DIR Setup to nDS Active DIR Hold from nDS Inactive ALE High Width ALE Low Width nDS Low Width nDS High Width nIOCS16 Hold Delay from ALE Low nIOCS16 Output Delay from ALE Low min 20 10 10 10 15 0 4TARB* 10 10 20 20 60 20 0 max units nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
40 20
40
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
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AD0-AD2, D3-D15
VALID t1 t2, t4 t3
VALID DATA
nCS t10 t6
ALE nRD
t9 t5
t7
nWR
t13 Note 3 t14 t15 Invalid
t11
t8 t12 Note 2 Valid Value
nIOCS16
Previous Value
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nRD Low nRD Low to Valid Data nRD High to Data High Impedance Cycle Time (nRD Low to Next Time Low) ALE High Width ALE Low Width nRD Low Width nRD High Width nWR to nRD Low nIOCS16 Hold Delay from ALE Low nIOCS16 Output Delay from ALE Low min 20 10 10 10 15 0 4TARB* 20 20 60 20 20 0 max units nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
40 20
40
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from Data Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
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AD0-AD2, D3-D15 t1 nCS
VALID t2, t4 t3
VALID DATA
t12 t7 Note 2 t8** t14 t10 Invalid MUST BE: BUSTMG pin = HIGH Parameter min 20 10 10 10 15 30 10 4TARB* 10 10 20 20 20 20 0 max units nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Valid Value t8
ALE nDS
t11 t5 t6 t13 t16 t9 t15
DIR
nIOCS16
Previous Value
40 * TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits The Microcontroller typically accesses the COM20022 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. ** Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nDS to the leading edge of the next nDS. Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer.
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16
Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low Valid Data Setup to nDS High Data Hold from nDS High Cycle Time (nDS to Next )** DIR Setup to nDS Active DIR Hold from nDS Inactive ALE High Width ALE Low Width nDS Low Width nDS High Width nIOCS16 Hold Delay from ALE Low nIOCS16 Output Delay from ALE Low
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle
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AD0-AD2, D3-D15 t1 nCS
VALID t2, t4 t3
VALID DATA
t10 t7 Note 2 t8** t12 t8
ALE nWR
t9 t5 t6 t15
nRD
t13 Note 3 t14
t11
nIOCS16
Previous Value
Invalid
Valid Value
MUST BE: BUSTMG pin = HIGH Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low Valid Data Setup to nDS High Data Hold from nDS High Cycle Time (nWR to Next )** ALE High Width ALE Low Width nWR Low Width nWR High Width nRD to nWR Low nIOCS16 Hold Delay from ALE Low nIOCS16 Output Delay from ALE Low min 20 10 10 10 15 30 10 4TARB* 20 20 20 20 20 0 max units nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
40
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits The Microcontroller typically accesses the COM20022 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. ** Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nWR to the leading edge of the next nWR. Write cycle for Address Pointer Low Register occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
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A0-A2 t1 nCS
VALID t2
t3 nRD nWR D0-D15 nIOCS16 t11 Note 3 t10 t6 VALID DATA VALID VALUE CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Address Setup to nRD Active Address Hold from nRD Inactive nCS Setup to nRD Active nCS Hold from nRD Inactive Cycle Time (nRD Low to Next Time Low) nRD Low to Valid Data nRD High to Data High Impedance nRD Low Width nRD High Width nWR to nRD Low nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min 15 10 5** 0 4TARB* 0 60 20 20 0**** 40** 20 max t5 t8
t4
t7
t9 Note 2
t12
units nS nS nS nS nS nS nS nS nS nS nS nS
40***
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits ** nCS may become active after control becomes active, but the access time (t6) will now be 45nS measured from the leading edge of nCS. *** t11 is measured from the latest active (valid) timing among nCS, A0-A2. **** t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from Data Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
A0-A2 t1 nCS
VALID t2
t3 nRD nWR D0-D15 nIOCS16 t11 Note 3 t10 t6 VALID DATA VALID VALUE CASE 2: BUSTMG pin = LOW or RBUSTMG bit = 1 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Address Setup to nRD Active Address Hold from nRD Inactive nCS Setup to nRD Active nCS Hold from nRD Inactive Cycle Time (nRD Low to Next Time Low) nRD Low to Valid Data nRD High to Data High Impedance nRD Low Width nRD High Width nWR to nRD Low nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min -5 0 -5 0 4TARB*+30 0 100 30 20 0**** 60** 20 max t5 t8
t4
t7
t9 Note 2
t12
units nS nS nS nS nS nS nS nS nS nS nS nS
40***
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits ** t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2. *** t11 is measured from the latest active (valid) timing among nCS, A0-A2. **** t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from Data Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
A0-A2 t1 nCS t3 DIR nDS t8 D0-D15 t12 t5
VALID t2
t4 t7 t6 t10 t9 VALID DATA t11 Note 2
t13
nIOCS16
VALID VALUE CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to nDS Active nCS Hold from nDS Inactive DIR Setup to nDS Active Cycle Time (nDS Low to Next Time Low) DIR Hold from nDS Inactive nDS Low to Valid Data nDS High to Data High Impedence nDS Low Width nDS High Width nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min 15 10 5** 0 10 4TARB* 10 0 60 20 0**** max units nS nS nS nS nS nS nS nS nS nS nS nS nS
40** 20
40***
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits ** nCS may become active after control becomes active, but the access time (t8) will now be 45nS measured from the leading edge of nCS. *** t12 is measured from the latest active (valid) timing among nCS, A0-A2. **** t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
A0-A2 t1 nCS t3 DIR nDS t8 D0-D15 nIOCS16 t12 t5
VALID t2
t4 t7 t6 t10 t9 VALID DATA VALID VALUE t11 Note 2 t13
CASE 2: BUSTMG pin = LOW or RBUSTMG bit = 1 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to nDS Active nCS Hold from nDS Inactive DIR Setup to nDS Active Cycle Time (nDS Low to Next Time Low) DIR Hold from nDS Inactive nDS Low to Valid Data nDS High to Data High Impedence nDS Low Width nDS High Width nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min -5 0 -5 0 10 4TARB*+30 10 0 100 30 0**** max units nS nS nS nS nS nS nS nS nS nS nS nS nS
60** 20
40***
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits ** t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2. *** t12 is measured from the latest active (valid) timing among nCS, A0-A2. **** t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
A0-A2 t1 nCS
VALID t2 t4
nRD nWR
Note 3 t10
t3 t8
t9 t5 Note 2 t5**
t11 D0-D15 nIOCS16
t6 VALID DATA VALID VALUE
t7
t12
CASE 1: BUSTMG pin = HIGH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Parameter Address Setup to nWR Active Address Hold from nWR Inactive nCS Setup to WR Active nCS Hold from nWR Inactive Cycle Time (nWR to Next )** Valid Data Setup to nWR High Data Hold from nWR High nWR Low Width nWR High Width nRD to nWR Low nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min 15 10 5 0 4TARB* 30*** 10 20 20 20 0***** max units nS nS nS nS nS nS nS nS nS nS nS nS
40****
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits ***: nCS may become active after control becomes active, but the data setup time will now be 30 nS measured from the later of nCS falling or Valid Data available. **** t11 is measured from the latest active (valid) timing among nCS, A0-A2. ***** t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. **Note 2: Any cycle occurring after a write to the Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nWR to the leading edge of the next nWR. Write cycle for Address Pointer Low Register occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
A0-A2 t1 nCS
VALID t2 t4
nRD nWR
Note 3 t10
t3 t8
t9 t5 t5** Note 2 t7 t12
t11 D0-D15 nIOCS16
t6 VALID DATA VALID VALUE
CASE 2: BUSTMG pin = LOW t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Parameter Address Setup to nWR Active Address Hold from nWR Inactive nCS Setup to WR Active nCS Hold from nWR Inactive Cycle Time (nWR to Next )** Valid Data Setup to nWR High Data Hold from nWR High nWR Low Width nWR High Width nRD to nWR Low nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min 0 0 0 0 4TARB* 30 10 65 30 20 0***** max units nS nS nS nS nS nS nS nS nS nS nS nS
40****
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits **** t11 is measured from the latest active (valid) timing among nCS, A0-A2. ***** t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. The Microcontroller typically accesses the COM20022 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. ** Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nWR to the leading edge of the next nWR. Write cycle for Address Pointer Low Register occurring after a write to Data Register requires a minimum of 5TARB from the trailing edge of nWR to the leading edge of the next nWR. Write cycle for Address Pointer Low Register occurring after a read from Data Note 3: Register requires a minimum of 5TARB from the trailing edge of nRD to the leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
t12 nIOCS16 A0-A2 t1 nCS t4 DIR t3 t5 nDS t10 t8 D0-D15 VALID DATA CASE 1: BUSTMG pin = HIGH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Parameter Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to nDS Active nCS Hold from nDS Inactive DIR Setup to nDS Active Cycle Time (nDS to Next Time )** DIR Hold from nDS Inactive Valid Data Setup to nDS High Data Hold from nDS High nDS Low Width nDS High Width nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min 15 10 5 0 10 4TARB* 10 30*** 10 20 20 0***** max units nS nS nS nS nS nS nS nS nS nS nS nS nS t9 t7 t11 Note 2 t6** VALID t2 VALID VALUE
t13
t6
40****
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits ***: nCS may become active after control becomes active, but the data setup time will now be 30 nS measured from the later of nCS falling or Valid Data available. ****: t12 is measured from the latest active (valid) timing among nCS, A0-A2. *****: t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. The Microcontroller typically accesses the COM20022 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. **Note 2: Any cycle occurring after a write to the Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nDS to the leading edge of the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
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DATASHEET
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
t12 nIOCS16 A0-A2 t1 nCS t4 DIR t3 t5 nDS t10 t8 D0-D15 VALID DATA CASE 2: BUSTMG pin = LOW t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Parameter Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to nDS Active nCS Hold from nDS Inactive DIR Setup to nDS Active Cycle Time (nDS to Next )** DIR Hold from nDS Inactive Valid Data Setup to nDS High Data Hold from nDS High nDS Low Width nDS High Width nIOCS16 Output Delay from nCS Low nIOCS16 Hold Delay from nCS High min 0 0 0 0 10 4TARB* 10 30 10 65 30 0***** max units nS nS nS nS nS nS nS nS nS nS nS nS nS t9 t7 t11 Note 2 t6** VALID t2 VALID VALUE
t13
t6
40****
* TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 TARB is twice Topr if SLOW ARB = 1 Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits **** t12 is measured from the latest active (valid) timing among nCS, A0-A2. ***** t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2. Note 1: The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. **Note 2: Any cycle occurring after a write to the Address Pointer Low Register requires a minimum of 4TARB from the trailing edge of nDS to the leading edge of the next nDS. Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
nTXEN t4 t1 nPULSE1 LAST BIT (400 nS BIT TIME) t1 nPULSE2 t2 t2 t5
t3
t6 RXIN Parameter t1 t2 t3 t4 t5 t6 t7 t8
t8
t7 min typ 100 400 0 100 400 max units nS nS nS nS nS nS nS nS
nPULSE1, nPULSE2 Pulse Width nPULSE1, nPULSE2 Period nPULSE1, nPULSE2 Overlap nTXEN Low to nPULSE1 Low Beginning of Last Bit Time to nTXEN High RXIN Active Pulse Width RXIN Period RXIN Inactive Pulse Width
-10 850 250 10 20
+10 950 350
Note: Use Only 2.5 Mbps
Figure 8.13 - Normal Mode Transmit or Receive Timing (These signals are to and from the hybrid)
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
nTXEN t1 t3 nPULSE1 t9 t4 nPULSE2 (Internal Clk) t5 t7 t6 t2 LAST BIT (400 nS BIT TIME) t8 t13
t10 RXIN t11 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t13 t10 t11 t12
t12
min -25
typ 200* 400*
max 50
units nS nS nS nS nS nS nS nS nS nS nS nS nS
nPULSE2 High to nTXEN Low nPULSE1 Pulse Width nPULSE1 Period nPULSE2 Low to nPULSE1 Low nPULSE2 High Time nPULSE2 Low Time nPULSE2 Period nPULSE2 High to nTXEN High (First Rising Edge on nPULSE2 after Last Bit Time) nTXEN Low to first nPULSE1 Low** Beginning Last Bit Time to nTXEN High** RXIN Active Pulse Width RXIN Period RXIN Inactive Pulse Width
-25
50 100* 100* 200*
-25 650 450 10 20 200* 400*
50 750 550
Above values are for 2.5 Mbps. Other Data Rates are shown below. TDR is the Data Rate Period *t5, t6 = TDR/4 *t2, t7, t10 = TDR/2 *t3, t11 = TDR 7 **t9 = 4 x TDR +/- 50 nS **t13 =
5 4
x TDR +/- 50 nS
Figure 8.14 - Backplane Mode Transmit or Receive Timing (These signals are to and from the differential driver or the cable)
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
4.0V XTAL1
t1 1.0V Parameter
t2
t3 50% of VDD
min 20 20 50 10 -200
typ
max
t1 t2 t3 t4 t5
Input Clock High Time Input Clock Low Time Input Clock Period* Input Clock Frequency* Frequency Accuracy*
100 20 200
units nS nS nS MHz ppm
Note*: Input clock frequency must be 20 MHz (+100ppm or better) to use the internal Clock Multiplier. t4 and t5 are applied to crystal oscillaton.
Figure 8.15 - TTL Input Timing on XTAL1 Pin
t1 nRESET
nINTR t2 Parameter t1 t2 nRESET Pulse Width*** nINTR High to Next nINTR Low EF = 0 EF = 1 min 5TXTL* TDR**/2 4TXTL* typ max units
Note*: TXTL is period of external XTAL oscillation frequency. Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS) Note***: When the power is turned on, t1 is measured from stable XTAL oscillation after VDD was over 4.5V.
Figure 8.16 - Reset and Interrupt Timing
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
nCS t19 t20
t19
t20
t10 nREFEX t3 t26 t3
DREQ t2 t21 nDACK
t6 t5 t4
t7*
t1 t24 t25 t24 t25
TC
t15
nWR t11 Write LOW-POINTER when DMAEN=1 t12 t8 DATA (D15-D0) t9 VALID t16
nRD
t14
t13 t17 t18
VALID
Note*: t7 is measured from the latest active timing among TC, Write/Read.
Figure 8.17 - DMA Timing (Intel Mode 80XX)
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
nCS t19 t20
t19
t20
t10 nREFEX t3 t26 t3
DREQ t2 t21 nDACK
t6 t5 t4
t7*
t1 t24 t25 t24 t25
TC t15 t16
DIR t22
VALID t11 t23
VALID t22 t23
nDS t12 Write LOW-POINTER when DMAEN=1 DATA (D15-D0) t8 t9 VALID t14 t13 t17 t18
VALID
Note*: t7 is measured from the latest active timing among TC, Write/Read.
Figure 8.18 - DMA Timing (Motorola Mode 68XX)
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Table 8.1 - DMA Timing
t1 t2 t3 t4 t5
PARAMETER nDACK Inactive Pulse Width The First DREQ Assertion Delay After Writing Low Pointer
MIN
TYP
4 Tarb 0 0
7Txtl 15Txtl
5 Tarb
DREQ Assert Delay from nREFEX Active at Programmable Burst Transfer Mode DREQ Assertion Delay from Write/Read Inactive at NonBurst Transfer Mode GTTM DREQ Assertion Delay from nDACK bit =0 Inactive due to Timeout of Gate Timer GTTM bit=1 at Programmable Burst Transfer Mode DREQ Negation Delay from Write/Read Active DREQ Negation Delay from TC and Write/Read Active Data Access Time from Read Active Data Float Delay from Read Inactive nREFEX Active Pulse Width Write Active Pulse Width CASE 1W CASE 2W CASE 1R
MAX 30 5Tarb +40ns 40
UNIT
NOTE
ns Note 1 ns ns Note 3 Note 4 Note 2
40
8Txtl +40ns 16Txtl +40ns
t6 t7 t8 t9 t10 t11
0 0 0 20 20 65 60 100 20 20 30 4Tarb 4Tarb
4Tarb+3 0nS
40 40 40 20
ns ns ns ns ns ns ns ns ns ns ns ns
Note 4 Note 4 Note 4 Note 4 Note 4,5 Note 4,5 Note 4 Note 4,5 Note 1,4 Note 1,4,5
t12
Read Active Pulse Width
t13 t14 t15 t16
CASE 2R Active Pulse Overlap Width between TC and Write/Read Write/Read Inactive Pulse Width CASE1w/1R CASE2w/2R Write Cycle Interval Period Read Cycle Interval Period CASE1R CASE2R
t17 t18 t19 t20 t21 t22 t23 t24 t25 t26
Data Setup to Write Inactive Data Hold From Write Inactive nCS High Setup to nDACK Active nCS High Hold from nDACK Inactive DREQ Active Setup to nDACK Active DIR Setup to nDS Low (Motorola mode only) DIR Hold from nDS High (Motorola mode only) nDACK Setup to Write/Read Active nDACK Hold After Write/Read Inactive nREFEX Inactive Time
30 10 20 20 20 10 10 30 5
3Txtl
ns ns ns ns ns ns ns ns ns
Note 4 Note 4
Note 4 Note 4 Note 2
Notes: 1. Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit. SLOWARB must set to "1" if the data rate is over 5 Mbps. (i.e. 10 Mbps) Tarb is Topr at SLOWARB=0 and Tarb is 2Topr at SLOWARB=1. Topr is the period of Operation Clock Frequency. It depends on the CKUP1 and CKUP0 bits. 2. Txtl is a period of external XTAL oscillation frequency.
3.
The nREFEX pin must not be Low while nDACK is Low.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
4.
5.
"Write" means write signal and "Read" means read signal. "Write/Read" means write or read signal. At INTEL MODE, write signal is nWR and read signal is nRD. At MOTOROLA MODE, write signal is nDS when DIR is Low and the read signal is nDS when DIR is High. Conditions of CASE1W, CASE2W, CASE1R and CASE2R are shown below; CASE1W : BUSTMG pin = High CASE2W : BUSTMG pin = Low CASE1R : BUSTMG pin = High and RBUSTMG bit = 0 CASE2R : BUSTMG pin = Low or RBUSTMG bit = 1
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 9
Package Outline
Figure 9.1 - COM20022I 48 Pin TQFP Package Outline Table 9.1 - COM20022I 48 Pin TQFP Package Parameters A A1 A2 D D/2 D1 E E/2 E1 H L L1 e W R1 R2 ccc ccc MIN ~ 0.05 1.35 8.80 4.40 6.90 8.80 4.40 6.90 0.09 0.45 ~ NOMINAL ~ 0.10 1.40 9.00 4.50 7.00 9.00 4.50 7.00 ~ 0.60 1.00 0.50 Basic ~ ~ ~ ~ ~ ~ MAX 1.6 0.15 1.45 9.20 4.60 7.10 9.10 4.60 7.10 0.20 0.75 ~ REMARK Overall Package Height Standoff Body Thickness X Span 1 /2 X Span Measure from Centerline X body Size Y Span 1 /2 Y Span Measure from Centerline Y body Size Lead Frame Thickness Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity (Assemblers) Coplanarity (Test House)
0o 0.17 0.08 0.08 ~ ~
7o 0.27 ~ 0.20 0.0762 0.08
Notes: 1. Controlling Unit: millimeter 2. Tolerance on the position of the leads is 0.04 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. 5. Details of pin 1 identifier are optional but must be located within the zone indicated.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 10 Appendix A
This appendix describes the function of the NOSYNC and EF bits.
10.1
NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by enabling or disabling the SYNC command during initialization. It is defined as follows: NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not have to be idle for the RAM initialization sequence to be written. The following discussion describes the function of this bit: During initialization, after the CPU writes the Node ID, the COM20022I will write "D1"h data to Address 000h and Node-ID to Address 001h of its internal RAM within 3uS. These values are read as part of the diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will report it as a device diagnostic failure. These writes are controlled by a micro-program which sometimes waits if the line is active; SYNC is the micro-program command that causes the wait. When the microprogram waits, the initial RAM write does not occur, which causes the diagnostic error. Thus in this case, if the line is not idle, the initialization sequence may not be written, which will be reported as a device diagnostic failure. However, the initialization sequence and diagnostics of the COM20022I should be independent of the network status. This is accomplished through some additional logic to decode the program counter, enabled by the NOSYNC bit. When it finds that the micro-program is in the initialization routine, it disables the SYNC command. In this case, the initialization will not be held up by the line status. Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to be written.
10.2
EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follows: EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the new internal operation timing (the timing is the same as in the COM20020 Rev. B); EF=1: Enable the new internal operation timing. The EF bit controls the following timing/logic refinements in the COM20022I: a) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt and Clear Flag command and by reading the Next-ID register. This minimum disable time is changed by the Data Rate. For example, it is 200nS at 2.5Mbps and 50nS at 10Mbps. The 50nS width will be too short to for the Interrupt to be seen. Setting the EF bit will change the minimum disable time to always be more than 200nS even if the Data Rate is 10Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock is always 20MHz even if the data rate is 10Mbps.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
b)
Synchronize the Pre-Scalar Output
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Setup1 register. The CKP3-1 bits are changed by writing the Setup1 register from outside the CPU. It's not synchronized between the CPU and COM20022I. Thus, changing the CKP2-0 timing does not synchronize with the internal clocks of Pre-Scalar, and changing CKP2-0 may cause spike noise to appear on the output clock line. Setting the EF bit will include flip-flops inserted between the Setup1 register and Pre-Scalar for synchronizing the CKP2-0 with Pre-Scalar's internal clocks. Never change the CKP2-0 when the data rate is over 5 Mbps. They must all be zero. c) Shorten The Write Interval Time To The Command Register
The COM20022I limits the write interval time for continuous writing to the Command register. The minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 S at the 156.25 Kbps. This 1.6 S is very long for CPU. Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS. d) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20022I has a write prohibition period for writing the Enable Transmit/Receive Commands. This period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by setting the TA/RI bit with an internal pulse signal. It is 3.2 S at 156.25 Kbps. This period may be a problem when using interrupt processing. The interrupt occurs when the RI bit returns to High. The CPU writes the next Enable Receive Command to the other page immediately. In this case, the interval time between the interrupt and writing Command is shorter than 3.2 S. Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1 on the following page.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
EF=0 Tx/Rx completed TA/RI bit Internal Setting Pulse nINTR pin prohibition period EF=1 Tx/Rx completed TA/RI bit Internal Setting Pulse nINTR pin
Figure 10.1 - Effect of the EF Bit on the TA/RI Bit
The EF bit also controls the resolution of the following issues from the COM20020 Rev B: a) Network MAP Generation
Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent node. Every time the Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to have deep knowledge of how the COM20022I works. Duplicate-ID is mainly used for generating the Network MAP. This has the same issue as Tentative-ID. A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when the COM20022I detects a write operation to Tentative-ID or Node-ID register. With this change, programmers can use the Tentative-ID or Duplicate-ID for generating the network MAP without any issues. This change is Enabled/Disabled by the EF bit. b) Mask Register Reset
The Mask register is reset by a soft reset in the COM20020 Rev. A, but is not reset in Rev. B. The Mask register is related to the Status and Diagnostic register, so it should be reset by a soft reset. Otherwise, every time the soft reset happens, the COM20020 Rev. B generates an unnecessary interrupt since the status bits RI and TA are back to one by the soft reset. This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register. This solution is Enabled/Disabled by the EF bit.
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet
Chapter 11 Appendix B: Example of Interface Circuit Diagram to ISA Bus
ISA Bus
LS688x nG 12 bit Comparator Q P=Q 12 LS245x A 16 bit Transceiver 12 I/O Address Seeting (DIP
AEN
SA15-
P
COM2002I nCS
SD1516
A
B 16 nG
D15-D0
DIR
nIOR nIOW SA23 IRQm 5V 3
nRD nWR A2-A0 nINTR
nIOCS16 DRQn nDACK TC nREFRES
nIOCS16 DREQ nDACK TC nREFEX
RESETDR
nRESET
Schmitt-Trigger Open-Collector
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DATASHEET

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